3


Reducing Barriers to Sustainable and Resilient Semiconductor Production

In addition to a review of the competitive position of the U.S. semiconductor sector, the committee was asked to review barriers to sustainable and resilient U.S. semiconductor production, including the factors that drive production and create reliable supply chains for equipment, components, and talent. This topic is discussed in this chapter with a particular focus on the Department of Defense’s (DoD’s) semiconductor sector needs and its potential role in strengthening this system.

In 2006, DoD’s Defense Science Board (DSB)¹ observed that three categories of electronics or semiconductor capabilities are relevant to national security electronics requirements: semiconductors used in applications where chips do not create a strategic competitive advantage; commercial (dual-use) leading-edge semiconductors whose use in military applications is vital to the performance of that equipment; and military-specific (defense-unique) semiconductors that are required to create leading-edge capabilities for defense systems. Only the latter two categories are primarily relevant to DoD concerns about maintaining its qualitative technological superiority relative to potential adversaries.

The previous discussion makes clear that, in contrast to the situation in 2006, the availability of leading-edge, dual-use semiconductors (the second category above) for use in DoD systems can no longer be taken for granted. In 2006, the DSB noted that state-of-the-art (SOTA) semiconductor fabrication plants (fabs)

___________________

¹ See Chapter 4 in U.S. Defense Science Board (DSB), 2006, Joint US Defense Science Board-UK Defence Scientific Advisory Council Task Force on Defense Critical Technologies, March, https://dsb.cto.mil/reports/2000s/ADA446196.pdf.

“are being established in the Far East” and that the United States “no longer has the asymmetric technology advantage that it once had.” The report went on to note that the “United States is not behind. But it is no longer as far ahead as it once was. One consequence of this is that the SOTA COTS [commercial-off-the-shelf] technology is available to U.S. adversaries.” In contrast to the situation observed in 2006, the committee believes that the United States is clearly now behind in leading-edge semiconductor fabrication, and the asymmetric technological advantage in semiconductor manufacturing resides outside the borders of the United States. Intel is striving to catch up on the most advanced chips, but DoD will also need to partner with the international firms that today provide the most advanced leading-edge microelectronics. This will require DoD to balance its desire to procure secure and “trusted” chips with its desire to field systems that have the most advanced chips. In a situation of continuing foreign company leadership, it can have one or the other, it cannot have both in the same chip.

The 2006 DSB task force went on to note that while some worried that the United States “will not have an assured and trusted supply of SOTA integrated circuits (ICs),” the task force’s view was that “in the next 10–20 years, wafer manufacturing in the United States will remain sufficiently strong to support DoD needs in the event of supply disruption in the Far East. One key reason is that the cost of wafer fab in the Far East is not substantially cheaper than the cost of wafer fab in the United States. Wafer fab costs are dominated by capital depreciation, and low cost labour [sic] has minimal impact on wafer fab cost.”²

The DSB task force did not in 2006 foresee the large subsidies to capital investment in semiconductor manufacturing that the U.S. semiconductor industry argues have been deployed by foreign competitor nations. Wafer fab costs, it appears, now are cheaper in other nations, due in large part to national industrial policies. The DSB in 2006 recommended that “DoD should also monitor the number of new U.S.-based fabs and provide incentives for U.S. companies to locate fabs in the United States as required.”³ In the year following the release of this report (2007), 16 percent of global semiconductor wafer fab capacity was located in the United States.⁴ By 2022, that figure was down to 10 percent,⁵ the U.S. share of fabs using more modern equipment, processing 300 mm wafers, was 8 percent,⁶ and the U.S.

___________________

² DSB, 2006, “Joint Task Force on Critical Technologies,” pp. 67–68.

³ DSB, 2006, “Joint Task Force on Critical Technologies,” p. 70.

⁴ National Research Council, 2012, Rising to the Challenge: U.S. Innovation Policy for the Global Economy, Washington, DC: The National Academies Press, https://doi.org/10.17226/13386, p. 340.

⁵ Semiconductor Industry Association (SIA) and Boston Consulting Group (BCG), 2024, “Emerging Resilience in the Semiconductor Supply Chain,” SIA, May, https://www.semiconductors.org/wp-content/uploads/2024/05/Report_Emerging-Resilience-in-the-Semiconductor-Supply-Chain.pdf, p. 14

⁶ SEMI 300mm Fab Outlook to 2026, cited at https://www.statista.com/chart/31371/distribution-of-global-semiconductor-fabricating-capacity.

share of fab capacity using leading-edge (less than 10 nm) technology nodes was 0 percent.⁷

The challenge at hand is how to construct a system of incentives that guarantees DoD and U.S. industry continued access to at least one leading-edge, high-volume commercial foundry within the United States over the next 10–20 years, and the continuing development of follow-on advanced chip manufacturing technology onshore beyond the 5-year time horizon of the CHIPS and Science Act of 2022 (CHIPS Act).

As previously discussed, the new generations of semiconductor chips are no longer getting cheaper at the rates they did under the era of Moore’s Law scaling paradigm. However, increased transistor miniaturization and lower-energy consumption continue to advance. For DoD, lowering the energy required for computations is now critical for placing greater intelligence in munitions or piloting drones and autonomous systems. In fact, DoD has a clear need to adopt chip architectures that enable lower energy use, greater density, and lower weight for the computing and artificial intelligence it will be embedding in its most advanced systems. Making it easier and cheaper to design and implement new systems and software and realize those designs with the most advanced chip manufacturing technology nodes is a growing DoD priority.

Achieving the outcomes DoD requires means overcoming a series of barriers to those outcomes. The most critical are described below.

OVERCOMING BARRIERS TO MANUFACTURING

Because it requires low volumes, and sometimes customization of chips, DoD is not in a good position to make demands on an industry that mainly relies on producing very large volumes of standardized chips. On the other hand, there is good reason to believe that there are many specialized new commercial chip designs targeting lower-volume markets that have shifted away from utilizing the most advanced available fabrication technology as Moore’s Law slowed.⁸

___________________

⁷ SIA and BCG, 2024, “Emerging Resilience in the Semiconductor Supply Chain,” p. 14.

⁸ As fixed design and mask costs for leading-edge fabrication technology nodes have increased, new low-volume applications have sometimes found mature, older fabrication technology to be the most economic choice. This resulted in a post-2014 “reawakening” wave of fabrication capacity investment using older vintage equipment from more mature technology nodes (e.g., fabrication equipment compatible with smaller 200 mm wafers). See the discussion in K. Flamm, 2021, “Measuring Moore’s Law: Evidence from Price, Cost, and Quality Indexes,” pp. 447–448 in Measuring and Accounting for Innovation in the 21st Century (C. Corrado, J. Miranda, J. Haskel, and D. Sichel, eds.), NBER and University of Chicago, https://www.nber.org/system/files/chapters/c13897/c13897.pdf.

Economic success in advanced chip manufacturing depends on a high-volume/low-mix business model, creating a fundamental challenge for DoD with respect to its needs for at least some custom, leading-edge, low-volume/high-mix, microelectronic components.⁹ If DoD-funded initiatives can make designing application-specific integrated circuit (ASIC) chips substantially less expensive using the most advanced fabrication technology nodes, as will be required for insertion of custom leading-edge chip technology into new defense systems, it could also have a substantial impact on the commercial chip industry. The same advances that make it less costly for DoD to design ASICs would also enable low-cost designs of commercial and industrial ASICs that use the most advanced available fabrication technologies.

DoD will need continuing access to leading-edge chips. Because U.S. firms have lost leadership in the most advanced logic chip production,¹⁰ it is important from both an economic and a national security perspective for the U.S. government to continue to encourage the current leaders, TSMC and Samsung, to create advanced manufacturing capabilities in the United States. At the time of writing, Intel is working to produce a new generation of advanced chips,¹¹ and TSMC and Samsung are now building new fabs in Arizona and Texas, respectively. Both TSMC and Samsung are expected to continue to produce the bulk of their chips in their home countries, but having at least some production capacity for the most advanced chips in the United States is important to DoD future technology needs.¹² Reflecting this, DoD has formed the new Office of Strategic Capital (OSC) to support the scale-up

___________________

⁹ In contrast to chip design costs, to some extent the rapidly increasing fixed costs of the masks (reticles) used to fabricate designs can be shared across different designs by bundling multiple designs together on a single multi-product “shuttle” wafer. The number of chip designs that can be bundled together on a single wafer is limited by the size of the mask (reticle) used to pattern a wafer. EUV reticles are currently limited in size to under 900 mm², and reticle size in upcoming new generations of equipment is likely to further decrease. See https://en.wikichip.org/wiki/mask.

¹⁰ M. Deutscher, 2023, “Intel Begins Mass-Producing Chips Using Cutting Edge EUV Technology,” Silicon Angle, September 29, https://siliconangle.com/2023/09/29/intel-begins-mass-producing-chips-using-cutting-edge-euv-technology; J. Laird, 2023, “Intel’s 18A ‘Hallelujah’ Moment Is the Biggest Bet the Company Has Ever Made,” November 13, https://www.pcgamer.com/intels-18a-hallelujah-moment-is-the-biggest-bet-the-company-has-ever-made.

¹¹ See, for example, M. Ahmad, 2023, “S Adds Two Variants to Its 2nm Node, Will Intel Catch Up?,” EDN, May 3, https://www.edn.com/tsmc-adds-two-variants-to-2-nm-node-will-intel-catch-up.

¹² CHIPS Act funding helped encourage this development, assisting in offsetting the 20 to 30 percent cost differential for production in the United States (largely from, as noted above, subsidies that competitor nations’ industrial policies provide to their semiconductor sectors). However, because CHIPS Act support expires in 5 years, a longer-term manufacturing perspective is required. This means that governmental financing for this differential likely needs to continue past this horizon. Continuation of at least the investment tax credit and loan guarantee programs in the CHIPS Act must therefore be considered.

and production of critical defense-relevant technologies. As stated in DoD’s Investment Strategy for the Office of Strategic Capital: Fiscal Year 2024:¹³

Provided it has sufficient resources, OSC could play an important role in the semiconductor ecosystem through provision of much-needed patient capital to bring new technologies to maturity.¹⁴ As stated earlier, a robust partnership between DoD and DOC is of the utmost importance to ensure continued support for U.S. manufacturing past the current CHIPS Act funding horizon.

Extension of Financing to Assure Continuing Advanced Chip Production

The CHIPS Act is a 5-year budget authorization, and there is no assurance that it will be extended, although the committee anticipates that the problems of U.S. chip leadership and the need for governmental financing to assure production capability in the United States will extend well beyond that. Therefore, DoD (with DOC) needs to consider ways to extend financing mechanisms for advanced semiconductor facilities over the longer term, including subsidies, loan guarantees, and investment tax credits. (See Recommendations 5.12 and 5.13.)

In this regard, it is worth recalling that the Defense Advanced Research Projects Agency (DARPA) was involved in creating the original foundry model, the Metal Oxide Semiconductor Implementation Service (MOSIS) for prototyping. DoD invested considerable resources in development of computer-aided design software tools and network infrastructure connecting university and industrial customers to semiconductor fabricators, utilizing design rules based on currently available fabrication technology and manufacturing processes. This DoD-underwritten infrastructure ultimately blossomed into the current commercial foundry ecosystem for both mature and leading-edge technology nodes. The foundry model now dominates the industry.

___________________

¹³ DoD, 2024, Investment Strategy for the Office of Strategic Capital: Fiscal Year 2024, https://www.cto.mil/wp-content/uploads/2024/05/OSC_FY24_Investment_Strategy.pdf, p. 1.

¹⁴ DoD, 2022, “Secretary of Defense Establishes Office of Strategic Capital,” December 1, https://www.defense.gov/News/Releases/Release/Article/3233377/secretary-of-defense-establishes-office-of-strategic-capital.

As a relatively low-volume customer aspiring to use leading-edge technology in its systems, DoD cannot avoid utilizing the foundry model it was so instrumental in creating in order to address its current semiconductor sourcing needs.

Extensions of the investment tax credit and loan guarantee programs can help assure DoD of continued access to an overall foundry manufacturing base in the United States for SOTA semiconductors. But then another issue arises: DoD also needs to work with specific semiconductor foundry companies to assure a supply that meets its particular needs for custom chips, including in emergencies. With few exceptions, the foundries that exist today to primarily meet DoD demand are not at the cutting-edge and therefore are not commercially competitive and lack high-volume, leading-node production.

To be commercially competitive and operating at the leading node, foundries cannot exist to primarily meet DoD needs. This reality requires DoD to forgo some of the security controls that it has historically required in hardware supply chains. Accepting some alternative control systems with additional information security risk that comes with these commercial partnerships is necessary given today’s status quo alternative, which limits DoD access to the most advanced chips it requires for defense systems. This challenge is discussed further in the section below on regulatory barriers.

Foundry Characteristics Needed for Department of Defense Access

DoD has several unique needs for U.S.-located foundries manufacturing leading-edge semiconductors, including dual-use production, ability to service high- and low-volume customers, competitive incentives to remain at the leading edge, sensitivity to international supply chains, and managing supply chain risks.

• Dual use. Only a manufacturer successfully serving commercial markets will have the volume needed to amortize the escalating cost of leading-edge fabrication facilities and R&D on the next generation of technology. Accordingly, DoD is incentivized to use foundries that are dual-use manufacturers, serving both DoD and commercial customers.
• High and low volume. Such a foundry will serve both high-volume and low-volume customers, for commercial and for defense needs. Economical production of low-volume chip designs at the leading edge (including prototype and research chips) is possible today when several designs are aggregated together onto a single, large, multi-project wafer, thus dividing the fixed costs of mask sets and production overhead cost among multiple projects.
• Maintaining competition. Ideally, there will be multiple foundry producers located in the United States or its trusted allies capable of serving both defense and commercial customers, competing freely against one another at the leading edge, including for DoD business. (The track record of sole-supplier

“national champions” in providing viable, competitive high-tech products is highly problematic.) Maintaining some significant degree of competition, with at least some of that leading-edge capability in the United States, is worth some additional cost from both the national security and economic security perspective.

• International supply chains. Increased economies of scale and the globalization of semiconductor infrastructure mean that geopolitical risks to supply chains can be managed but cannot be eliminated. Semiconductor industry companies headquartered in the United States, as well as companies headquartered in friendly nations, all rely on R&D groups and regional centers of excellence scattered around the globe. IBM’s development of metal-oxide-semiconductor (MOS) memory technology in the late 1960s and 1970s made critical use of a German research laboratory; some of Intel’s important processor designs were developed in Israel; equipment producer Applied Materials depends on its Finnish subsidiary for specialized expertise in atomic layer deposition and etch.¹⁵ Requiring that all components, expertise, and skills be sourced within national boundaries for national security reasons would be prohibitively expensive and would likely lead to a loss of technology leadership.
• Community solution. A coalition of “friends and allies” is an appropriate approach for managing supply chain risks to both national security and economic security.

Partnership Mechanisms for Department of Defense Fabrication Plant Access

DoD’s Rapid Assured Microelectronics Prototypes (RAMP) program and, more recently, its follow-on RAMP-C program illustrate approaches that DoD can apply in partnering with manufacturers to meet its chip needs.¹⁶ Starting in 2020, DoD’s RAMP program demonstrated how to securely obtain SOTA microelectronics technologies from industry without depending on a closed security

___________________

¹⁵ See S. Leibson, 2023, “A Brief History of the MOS Transistor, Part 3,” Electronic Engineering Journal, April 17, https://www.eejournal.com/article/a-brief-history-of-the-mos-transistor-part-4-ibm-research-persistence-and-the-technology-no-one-wanted; Intel, 2024, “About Intel Israel,” https://www.intel.com/content/www/us/en/corporate-responsibility/intel-in-israel.html; Applied Materials, Applied Materials Finland, https://www.appliedmaterials.com/eu/en/about/europe-overview/finland-overview.html.

¹⁶ See DoD, 2020, “Department of Defense Announces $197.2 Million for Microelectronics,” October 15, https://www.defense.gov/News/Releases/Release/Article/2384039/department-of-defense-announces-1972-million-for-microelectronics; Intel, 2023, “RAMP-C Program on Intel 18A Adds 2 Strategic Defense Industrial Base Customers,” July 18, https://www.intel.com/content/www/us/en/newsroom/news/ramp-c-program-intel-18a-adds-strategic-defense-industrial-base-customers.html.

architecture fabrication process or facility.¹⁷ In the 2023 RAMP-C program, Intel’s foundry program enabled two leading DoD systems suppliers, Boeing and Northrop Grumman, to use Intel’s upcoming 18A process technology and industry-standard design tools and intellectual property (IP) to develop and fabricate customized test chips for DoD in preparation for product insertions. Previously, RAMP-C included arrangements with Nvidia, Qualcomm, IBM, and Microsoft. DoD’s related State-of-the-Art Heterogeneous Integrated Packaging (SHIP) program focuses on packaging for prototype devices.¹⁸ These three programs—RAMP, RAMP-C, and SHIP—created innovative DoD contractual arrangements with companies to meet DoD microelectronics needs.

Occasionally, commercial customers for leading-edge semiconductors have entered into partnership agreements with semiconductor manufacturers, investing in those companies to ensure they have guaranteed access to needed chip supply to meet their business needs. Recent examples include the following: Tower Semiconductor making a capacity investment in an Intel fab line in New Mexico; Vitesco paying for new silicon carbide production capacity at an OnSemi fab; Qualcomm financing a capacity expansion by GlobalFoundries; and Sandisk investing in Toshiba capacity expansion.¹⁹ In these cases, customers were investing in semiconductor manufacturer capacity to ensure that their needs for manufactured semiconductor products would be met. There is no fundamental reason why DoD cannot fund a similar arrangement that serves the same essential purpose—ensuring that needed capacity to build leading-edge semiconductors for DoD use is available in the United States.

___________________

¹⁷ DoD, 2024, “Rapid Assured Microelectronics Prototypes Using Advanced Commercial Capabilities (RAMP) Project,” https://www.cto.mil/ramp-project.

¹⁸ DoD, 2023, “Department of Defense Celebrates Advancements in Microelectronics Capabilities,” April 6, https://www.defense.gov/News/Releases/Release/Article/3355049/department-of-defense-celebrates-advancements-in-microelectronics-packaging-cap.

¹⁹ Intel, 2023, “Intel Foundry Services and Tower Semiconductor Announce New Foundry Agreement,” Press Release, September 5, https://www.intc.com/news-events/press-releases/detail/1643/intel-foundry-services-and-tower-semiconductor-announce-new. For other examples, see Business Wire, 2023, “Bitesco Technologies and Onsemi Sign Long Term Supply Agreement,” May 31, https://www.businesswire.com/news/home/20230531005876/en/Vitesco-Technologies-and-onsemi-Sign-SiC-Long-Term-Supply-Agreement-and-Agree-to-Invest-in-SiC-Technology-Capacity-Expansion; The Register, 2022, “GlobalFoundries Double Down on US Chip Production,” Qualcomm, August 8, 2022, https://www.theregister.com/2022/08/08/globalfoundries_qualcomm_us; “AnandTech, Toshiba Memory and Western Digital Finalize Fab K1,” May 10, 2019, https://www.anandtech.com/show/14359/toshiba-memory-western-digital-finalize-fab-k1-investment-agreement; The Street, 2006, “Toshiba to Build Japanese Chip Plant,” SanDisk, August 4, https://www.thestreet.com/technology/sandisk-toshiba-to-build-japanese-chip-plant-10301922; Toshiba News Release, 2010, “Toshiba and SanDisk Sign Joint Venture Agreement,” July 14, https://www.global.toshiba/ww/news/corporate/2010/07/pr1401.html.

There are a variety of mechanisms that the government has historically used to subsidize the availability of capacity in the United States to meet potential defense needs in an emergency, including loan guarantees, air carrier capacity assurance, the Defense Production Act, and the government-owned, contractor-operated (GOCO) approach. These mechanisms are summarized below, and may have potential applicability to meeting DoD semiconductor needs.

• Loan guarantees. Loan guarantees from the government provide a form of subsidy to capital investments. The committee understands that this authority is under consideration in DoD through its new Office of Strategic Capital. If this new office develops its lending capability at sufficient scale, it may allow DoD to access semiconductor manufacturing capacity as needed.
• Air carrier capacity assurance. Under the Civil Reserve Air Fleet program, domestic commercial airlines contractually commit aircraft for potential DoD emergency use in return for peacetime DoD airlift business directed to the participating airlines.²⁰ Here, DoD leverages its ongoing spending on air transport through commercial air carriers to also assure a reserve air transport fleet. A conceptually similar approach to DoD’s semiconductor needs could be envisioned, although the current relatively low volume of DoD semiconductor purchases likely will not, by itself, yield enough leverage to motivate private chipmakers to guarantee later capacity access.
• Defense Production Act. The Defense Production Act of 1950 (DPA) is the legal foundation for application of U.S. commercial industrial might to DoD needs from the 1950s through the present day. It is a frequently wielded tool that DoD has used to align U.S. technology and industrial investments with national security needs in recent decades.²¹ The DPA created a framework

___________________

²⁰ U.S. Air Force, 2014, “Civil Reserve Air Fleet (CRAF),” July 2014, https://www.af.mil/About-Us/Fact-Sheets/Display/Article/104583/civil-reserve-air-fleet.

²¹ The U.S. Army first used procurement contracts to fund development of new manufacturing technology in the period after an early “national security shock,” the War of 1812. Responding to problems in securing supplies of needed firearms as European imports, the Army at first gave contracts to U.S. start-up firms to develop technology for the high-volume production of firearms with interchangeable parts, investing in facilities to mass produce them. These contracts typically advanced funds to contractors (initially, Eli Whitney’s factory in North Haven, Connecticut) to cover the development costs, as well as dual-use factory capital investments, that could then be utilized to sell these products to the government at negotiated prices. The Army’s arsenals at Harper’s Ferry, West Virginia, and Springfield, Massachusetts, took over the development R&D after Whitney’s efforts proved incomplete. Colt, Remington, and Smith and Wesson were all subsequent famous U.S. firearms start-ups that commercialized these products based on the interchangeable parts approach and the machine tools behind it. The new process initiated the creation of the “American system of manufactures,” homegrown industrial technology that powered U.S. manufacturing industries to global prominence in the 19th century and early 20th centuries. D. Hounshell, 1984, From the American System to Mass Production, 1800–1932: The Development of Manufacturing Technology in the United States, Johns Hopkins University Press; M. Roe Smith (ed.), 1985, Military Enterprise and Technological Change, MIT Press; M. Roe Smith, 1977, Harpers Ferry Armory and the New Technology, Cornell University Press.

that permits co-funding investments in industrial technology and production capacity investment for dual-use goods within the structure of DoD procurement contracts. DoD might consider running a competition for procurement contracts that would provide payment of some percentage of certain costs—for example, in a first phase, the costs of developing a next-generation, leading-edge fabrication technology node; in a second phase, the costs of building a commercial foundry capability in the United States. In exchange for DoD covering a percentage of the cost, the U.S. government would be contractually guaranteed priority access for up to that percentage of the capacity of the leading-edge industrial facility implementing this technology, on commercial terms. In normal times, the commercial firms would be authorized to sell unutilized defense foundry capacity to ordinary commercial users on normal terms. Outside of national security emergencies, the government would also pay for capacity on the same terms as commercial users. However, in times of emergency or urgent national security need, such foundries would be obligated contractually to accept Defense Production Allocation System (DPAS) DX- and DO-rated²² priority orders, on commercial terms, for up to the set percentage of the foundry’s production capacity (in new wafer starts), throughout the economic life of that foundry technology node. Capacity subsidy payments could be structured as progress payments on the relevant procurement contracts. Progress payments are an advanced financing tool that DoD has often used to fund big-ticket, risky, new technology and systems investment contracts intended to create innovative new defense systems.

• GOCO approach. DoD currently operates many GOCO facilities. The U.S. Air Force, for example, owns several aircraft manufacturing plants in which U.S. government facility investments are comingled with private contractor investments in production equipment and tooling. Examples include Air Force plants operated by Lockheed Martin in Fort Worth, Texas, and Marietta, Georgia (AF Plant 4 and AF Plant 6), where the F-35, F-16, F-22, C-6, C-130, and P-3 aircraft are produced, overhauled, or maintained. In addition to selling these aircraft to the U.S. government, the private contractors operating these facilities are permitted to make commercial sales to other customers.²³ The U.S. Army, in order to meet its need for ammunition plants, has also built plants, then contracted with private companies to operate these Army-owned plants. The company makes the product for commercial

___________________

²² DO-rated orders require the signature of the Under Secretary of Defense in charge of acquisition and technology; DX-rated orders require the signature of the Secretary of Defense. The order of priority is DX orders, then DO orders, then commercial. See Defense Contract Management Agency (DCMA), Defense Priorities and Allocation System (DPAS), Rating System, https://www.dcma.mil/DPAS.

²³ The government reportedly owns about 80 percent of the industrial facility floor space in these two plants, with the remainder, along with the industrial equipment and tooling, owned by the private contractor. See GlobalSecurity.org, Military, Air Force Plants 4 and 6, https://www.globalsecurity.org/military/facility/afp-4.htm, and https://www.globalsecurity.org/military/facility/afp-6.htm.

sales and makes modernization investments, but also supplies the military. The military, as plant owner, can preempt commercial sales to meet any emergency “surge” requirements.²⁴ The U.S. government has also invested in GOCO partnerships with private contractors to meet other national needs. Private contractors operate 16 out of 17 Department of Energy National Laboratories and are encouraged to make the capacity and capabilities of these laboratories available for sale to non-government customers. The National Institutes of Health (NIH) owns a private contractor–operated vaccine production facility that sells vaccines to private entities conducting clinical trials.²⁵ Because it is difficult to visualize a scenario in which DoD needs would ever amount to more than a small fraction of the output of a commercial volume foundry, majority government ownership seems excessive. However, an arrangement with the government owning a minority share, in exchange for access to capacity if needed, appears a reasonable arrangement.

Given that guaranteed supply of advanced semiconductors for use in U.S. military systems is arguably as critical to a 21st-century military as ammunition rounds were in the 20th century, all of these partnership mechanisms should be considered to assure DoD can obtain the chips it needs.

Leveraged Access for Department of Defense to Fabrication Plants

Semiconductor fabs only remain state-of-the-art for 3–5 years, until superseded by the next generation of advanced technologies and newer fabs. A lesson from the past two decades of semiconductor manufacturing is that advanced fabs will only be constructed in the United States if federal government financing matches that of competitor nations—the essential approach taken by the CHIPS Act. As suggested above, DoD could benefit from a collaborative agreement to meet its advanced chip needs as part of such government financing. That is, the government might finance a share of the new process technology development and fab construction in exchange for DoD obtaining guaranteed access to a share of the resulting new capacity. The U.S. government could combine a strategy for assuring U.S.-based manufacturing of advanced chips with a strategy for assuring DoD’s access to these facilities. (See Recommendation 5.13.)

___________________

²⁴ See, for example, L. McLaughlin, n.d., “Government-Owned, Contractor Operated 101,” BAE Systems, https://www.baesystems.com/en-us/feature/government-owned-contractor-operated-101.

²⁵ PrEP4All, 2022, “Deploying the Government Owned, Contractor Operated Model: How the U.S. Government Can Stand Up a Billion Dose mRNA Vaccine Facility Within Six Months,” Public Citizen, March 8, https://www.citizen.org/article/deploying-the-government-owned-contractor-operated-model.

OVERCOMING BARRIERS TO LOWER-COST DESIGN

The soaring costs of chip design for ASICs are a barrier to DoD using the highly integrated, customized chips to create technological superiority in military systems. This is the third category of chip discussed in the DSB’s 2006 report, namely, high-performance chips designed specifically for insertion into military systems to achieve technological advantage. This is not a new challenge: even in 2006, design costs for new custom chips were soaring, although not to the levels now seen. The 2006 DSB report’s very first recommendation was for an initiative to develop new design tools “to enable the design of affordable low volume, high performance custom ASICs.”²⁶ The logic driving that recommendation is even more relevant today.

In 2006, the DSB recommended that tool development

These observations remain true today. What has changed is that advances in software and artificial intelligence technology make very rapid progress more plausible today than it was 18 years ago.

The CHIPS Act focused on production facilities rather than on design costs. Significantly lowering design costs remains a critical barrier to DoD exploiting technology opportunities that would result from access to the most advanced chip manufacturing technology. Furthermore, DoD is not alone on this issue. Design cost at the most advanced technology nodes is a major challenge faced by start-ups and small and midsized firms, and large firms trying to tailor applications to relatively moderate-sized markets using the most advanced chips. Overall, many parts of industry have a significant interest in pursuing lower-cost design technologies. Thus, a collaborative R&D initiative led by DoD working with industry to develop lower-cost design approaches would also have broadly beneficial commercial impacts.

It is evident that human resource constraints increase costs and limit the insertion of advanced system semiconductors into new DoD systems. Use of AI and other tools may reduce the human input required for new advanced chip design and development perhaps by an order of magnitude. That is, the 300 to 400 software engineers required on a complex chip development effort potentially could be reduced to 30 or 40, and the 100 required on a simpler project could be reduced

___________________

²⁶ DSB, 2006, “Joint Task Force on Critical Technologies,” p. 69.

to 10. Overall, more efficient and lower-cost design represents a major technology challenge and DoD, in cooperation with the National Institute of Standards and Technology (NIST) and the National Semiconductor Technology Center (NSTC), would be well served by tackling this challenge. Progress in design automation will also assist in addressing the workforce training and supply issues discussed in Chapter 7. Furthermore, given the significant potential expected from advances in design automation, if the United States does not undertake this effort, it may well cede its current leadership in chip design to other nations. (See Recommendations 5.5, 5.6, and 5.7.)

OVERCOMING RESEARCH AND DEVELOPMENT BARRIERS TO NEXT-GENERATION SEMICONDUCTORS

In the R&D area, significant changes may be ahead for the semiconductor sector.²⁷ The effort to decrease CMOS-based²⁸ chip feature sizes has lasted for decades, but with node sizes reaching 3 nm, and potentially 2 or 1.5 nm, this approach is becoming increasingly difficult.²⁹ The need for post-CMOS technologies may arrive within the next decade.³⁰

New approaches involving different kinds of architectures, materials, packaging, software, and algorithms will be required. In general, the semiconductor industry needs to pursue three lines of effort to realize continued performance improvements for microelectronics: (1) more efficient architectures and packaging, (2) new models of computation, and (3) new materials and devices.³¹ The IEEE’s International Roadmap for Devices and Systems (IRDS) has identified a series of beyond-CMOS approaches, including the following: computational state variability, nonthermal equilibrium systems, novel energy transfer interactions, nanoscale thermal management, sublithographic management, and alternative architectures.³² Architecture advances that appear promising include in-memory

___________________

²⁷ Office of Science and Technology Policy (OSTP), 2024, “National Strategy for Microelectronics Research,” March, pp. 7–17.

²⁸ Complementary metal-oxide-semiconductor (CMOS) is a type of fabrication process for logic functions used for integrated circuit chips and first developed in 1963 and introduced in 1986 by Intel. See history in B. Lojek, 2007, History of Semiconductor Engineering, Berlin: Springer.

²⁹ M. Lapedus and E. Sperling, 2020, “Making Chips at 3nm and Beyond,” Semiconductor Engineering, April 16, https://semiengineering.com/making-chips-at-3nm-and-beyond.

³⁰ C. Leiserson, N. Thompson, J. Emer, B. Kuszmaul, B. Lampson, D. Sanchez, and T. Schardl, 2020, “There’s Plenty of Room at the Top: What Will Drive Computer Performance After Moore’s Law?,” Science 368:6495, https://www.science.org/doi/10.1126/science.aam9744.

³¹ J. Shalf, 2020, “The Future of Computing Beyond Moore’s Law,” Royal Society, https://royalsocietypublishing.org/doi/10.1098/rsta.2019.0061.

³² Institute of Electrical and Electronics Engineers (IEEE), 2018, “Beyond CMOS: The Future of Semiconductors,” IEEE IRDS, https://irds.ieee.org/home/what-is-beyond-cmos.

processing (to improve the power usage and performance of moving data between processor and memory), nano/micro electro-mechanical systems (N/MEMS), magneto-electric spin-orbit (MESO) logic devices, cryogenic electronics (low-temperature electronics), structures based on magnetic tunnel junctions, and edge computing (which processes data close to where it is generated, enabling greater speed and volume).³³ Use of 3D heterogeneous integration (3DHI) packaging (technologies that stack numerous integrated circuits and interconnect them vertically for improved performance at lower power and smaller size) is currently receiving attention, as described in more detail below. The 2022 report by DoD, “Future Directions Workshop: Materials, Processes, and R&D Challenges in Microelectronics,” emphasizes the need to explore scientific research in such areas as new materials for design approaches that involve alternatives to electron transport (including photonics, spintronics, topological materials, and exotic quasiparticles). In addition, new engineering processes could provide new materials approaches (including 3D integration, atomic scale fabrication and metrologies, and digital twins for semiconductor processes and microarchitectures). The report suggests new opportunities for post-CMOS advances.³⁴ (See Recommendations 5.2 and 5.3.)

During the 1950s and 1960s, faced with an apparent peer competitor, DoD made large investments in its industrial base and took risks in creating new weapons systems. DoD (and NASA)³⁵ encouraged its contractors to incorporate newly invented electronic devices into its systems even when reliability and performance were somewhat uncertain. Arguably, the security climate today is more like the 1960s than the 1990s, and DoD would be justified in absorbing a little more risk in exchange for increasing the odds of improvements in capability and quality. Advances in chip density, speed, and energy use are vitally important to DoD (as well as, of course, to many of the industries dependent on semiconductors). Industry leaders are focused more on the advances needed in the next decade, and less on subsequent technologies needed to maintain progress over the long term. DoD could play an important role in the coordination and support of these next-generation R&D efforts with industry, especially if funding for NSTC is not authorized past the initial 5 years.

An ongoing commitment to post-CMOS R&D appears in order; the NSTC may start to satisfy that need for the 5 years it has assured funding, and DoD should

___________________

³³ See also approaches detailed in DoD Basic Research Office, 2022, “Future Directions Workshop: Materials, Processes, and R&D Challenges in Microelectronics,” Department of Defense, June 23–24, https://basicresearch.defense.gov/Portals/61/Documents/future-directions/FDW%20Microelectronics%20Report_with%20DOI.pdf.

³⁴ S. Guha, H.S.P. Wong, J.A. Incorvia, and S. Chowdhury, 2022, “Future Directions Workshop: Materials, Processes, and R&D Challenges in Microelectronics,” Department of Defense, June 23–24.

³⁵ C. Fishman, 2020, One Giant Leap, New York: Simon and Schuster.

participate fully to ensure its concerns are met. DoD should also consider a separate effort for the longer-term support required and for its needs, in cooperation with the NSTC, building on the R&D elements within DARPA’s Electronic Resurgence Initiative (ERI) 2.0.³⁶

Leading-edge silicon semiconductor manufacturing technology is important because it is the hardware platform onto which new information technology (IT)—including not only new kinds of electronic components, but also new software and algorithms, photonics, AI, and quantum IT—is going to be incorporated into systems. However, metrics for progress in silicon MOS fabrication technology, such as the pace of improvement in speed, energy consumption, size, and density, have slowed relative to historical norms. The semiconductor device fabrication industry seems to have matured relative to its state just a decade or two in the past. Investments in software, AI, quantum information systems, and photonics may have both greater uncertainty and higher potential payoffs. It is important that DoD be positioned to take advantage of the latter.

In March 2024, the Subcommittee on Microelectronics Leadership of the National Science and Technology Council in the Office of the President released a strategy paper on microelectronics research.³⁷ The strategy focused on four areas: (1) accelerating research on future generations of advances on microelectronics; (2) building the research infrastructure, including tools and equipment, that can lead to prototyping and subsequent fabrication, assembly, packaging, and testing of new advances; (3) supporting the workforce that will be required both for research and implementation; and (4) creating the networks and activities that will support a robust innovation ecosystem in microelectronics. At the heart of the strategy is an aggressive pursuit of new R&D; the other three recommendations constitute supporting pillars for this effort. The R&D approach is multifaceted, calling for development of new processes and metrology for advanced packaging and integration; semiconductor materials that enhance capabilities and functionality; circuit design, simulation, and emulation tools; processing architectures and related hardware for future systems; manufacturing tools and processes for fabrication—all while prioritizing security as an element in design strategies. It also calls for improved access for start-ups, small firms, and university researchers to advanced facilities where they can prototype devices and processes. The issues identified in this report span both the needed short-term advances in packaging and integration as well as the longer-term advances listed in the National Science and Technology Council report, which can be generally described as post-CMOS

___________________

³⁶ DARPA, 2023, “Electronics Resurgence Initiative 2.0,” March 6, https://www.darpa.mil/work-with-us/electronics-resurgence-initiative.

³⁷ OSTP, 2024, “National Strategy for Microelectronics Research,” White House, March, https://www.whitehouse.gov/wp-content/uploads/2024/03/National-Strategy-on-Microelectronics-Research-March-2024.pdf.

technologies that are likely to be needed over the next decade. The recommendations that follow echo many of the specifics identified in the National Science and Technology Council strategy.

PACKAGING, INTEGRATION, AND OTHER NEAR-TERM TECHNOLOGIES

Progress is well under way on a set of semiconductor technology advances that could be realized in approximately 5 years. At the top of the list are efforts on packaging and integration, backed by both DARPA and NIST.

In late 2023, DARPA announced plans for a new center for Next-Generation Microelectronics Manufacturing (NGMM) to deliver new approaches for microelectronics fabrication. The center was initially funded at $430 million and is intended to undertake both research and prototyping, with a focus on the challenges of tomorrow and operating over longer timelines than efforts funded under the CHIPS Act. The premise is that by integrating and packaging chip components differently via 3DHI, manufacturers will be able to significantly improve performance. DARPA states:

The NGMM initiative recognizes that the semiconductor industry is shifting from mass-producing increasingly complex monolithic chips to creating chiplets that can be packaged together in three dimensions for customized applications.³⁹ According to Pat Gelsinger, CEO of Intel, “Essentially, old silicon stuff is becoming cool new packaging stuff. We’re now entering into the advanced-packaging era, where 2-and-a-half and 3D packages become the new norm.”⁴⁰ Recognizing the potential of this transition, Mark Rosker, director of DARPA’s Microsystems Technology Office, indicates the NGMM program is “looking at ways to incorporate photonics and non-silicon electronics into these systems.”⁴¹

___________________

³⁸ DARPA, 2023, “Next-Generation Microelectronics Manufacturing Aims to Sustain R&D Ecosystem: DARPA Names Eleven Teams to Kick Off Groundbreaking U.S. Chips-of-the-Future Effort,” July 20.

³⁹ Y. Jie, 2023, “To Drive AI, Chip Makers Stack ‘Chiplets’ Like Lego Blocks: Nvidia, Intel, AMD and Others Invest in Technology That Promises More-Powerful, Easier-to-Build Semiconductors,” Wall Street Journal, July 10.

⁴⁰ A. Boyle, 2023, “DARPA and Other Federal Agencies Working on Strategies to Revive America’s Chip Industry,” GeekWire, August 22, https://www.geekwire.com/2023/darpa-summit-revive-chip-industry.

⁴¹ Ibid.

NIST, too, is embarking on a major packaging and integration initiative with its National Advanced Packaging Manufacturing Program (NAPMP), funded with $3 billion from the CHIPS Act.⁴² Elements in the NAPMP program include materials and substrates; advances in tools, equipment, and processes; power delivery and thermal management; photonics and connectors; the chiplet ecosystem; and design using automated tools and built-in test and repair. Coordination of the DARPA and NIST programs will be important because elements of the two programs overlap.

DoD’s recently formed Microelectronics Commons (ME Commons), comprising a set of public–private partnerships (PPPs) to enable semiconductor technology transitions from laboratory to fabrication, to improve U.S. leadership in semiconductor technical development, and to accelerate the transition of new semiconductor technologies to domestic producers.⁴³ This 5-year CHIPS and Science Act program is aimed at six DoD semiconductor technology priorities: 5G and 6G broadband technology, AI and hardware, commercial leap-ahead technologies, electromagnetic warfare, Internet of Things and secure-edge computing, and quantum technology. It also aims to better connect university researchers in semiconductor fields with semiconductor production facilities to enable further research advances. Because of its somewhat shorter-term technology adoption focus, ME Commons is not positioned to address longer-term technologies.

NIST is forming the NSTC as a PPP consortium for semiconductor R&D and will engage academia and industry around barriers to technology advancement in the semiconductor industry, including workforce needs. The consortium will be a separate nonprofit corporation built around the consortia. The key strategic goals for the NSTC are to (1) extend U.S. leadership in foundational technologies for future applications and industries and strengthen the U.S. semiconductor manufacturing ecosystem, (2) significantly reduce the time and cost to prototype innovative ideas, and (3) build and sustain a semiconductor workforce development ecosystem.⁴⁴ The NSTC has the same 5-year timeline as other CHIPS Act programs.

___________________

⁴² NIST, 2023, “The Vision for the National Advanced Packaging Manufacturing Program,” CHIPS R&D Office, November 20, https://www.nist.gov/system/files/documents/2023/11/19/NAPMP-Vision-Paper-20231120.pdf. This packaging initiative was funded in the CHIPS and Science Act in 2022. See U.S. Senate Commerce Committee, The CHIPS Act of 2022, Section by Section Summary, https://www.commerce.senate.gov/services/files/592E23A5-B56F-48AE-B4C1-493822686BCB.

⁴³ DoD, 2024, “Microelectronics Commons,” https://microelectronicscommons.org.

⁴⁴ NIST, 2024, “National Semiconductor Technology Center,” July 12, https://www.nist.gov/chips/research-development-programs/national-semiconductor-technology-center. See also NIST, 2023, “NSTC Update to the Community,” November 16, https://www.nist.gov/chips/national-semiconductor-technology-center-update-community, and NIST, 2023, “A Vision and Strategy for the NSTC,” April 25, https://www.nist.gov/system/files/documents/2023/04/27/A%20Vision%20and%20Strategy%20for%20the%20NSTC.pdf.

Although NSTC’s existing appropriation is multiyear and can be stretched beyond 5 years, it is not clear whether that appropriation will be extended after that period, despite the expected needs. Because of their timelines, both the NSTC and ME Commons may naturally tend to focus on technologies that can be implemented in their 5-year periods.

The Need for Coordination Between the National Institute of Standards and Technology and the Department of Defense Near-Term Research and Development Programs

The establishment of DoD’s NGMM Center and ME Commons as well as NIST’s NAPMP and NSTC should enable substantial progress on the interim R&D agenda for semiconductor advances, including packaging and integration as well as other technologies that should be available for implementation in the coming half decade. It is vital that all these programs be effectively coordinated to assure exchange of ideas and avoid duplication and research dead ends. (See Recommendation 5.1.)

These programs should also assist in lowering another barrier to progress in semiconductor research—the need to provide university semiconductor researchers as well as start-up companies with access to advanced fabrication facilities. (See Recommendation 5.2.)

POST-COMPLEMENTARY METAL-OXIDE-SEMICONDUCTOR ADVANCES

In addition to the potential initial advances noted above, DoD needs to consider longer-range semiconductor technology advances that could evolve in the coming decade. Those are centered around post-CMOS technologies to achieve needed gains in speed, energy use, and density. As the semiconductor sector’s International Roadmap for Devices and Systems (IRDS) has found, “the future of the semiconductor industry is headed Beyond CMOS.”⁴⁵ Unless a systematic effort commences relatively soon, those technologies will not be accessible in approximately 10 or so years as the current scaling efforts play out.

Major gains are possible through a wide range of possible CMOS approaches, many of which are listed at the outset of this section on R&D barriers, as identified in the IRDS. This range gives researchers flexible options to pursue to come up with promising approaches. The Nanoelectronics Research Initiative (NRI) of the Semiconductor Research Corporation (SRC) is attempting to benchmark these potential

___________________

⁴⁵ IEEE, 2023, “Beyond CMOS: The Future of Semiconductors.”

approaches against each other.⁴⁶ There are also significant efficiency gains possible through software performance engineering, which entails restructuring software so computer applications can run more quickly by removing unneeded software elements and tailoring software to specific features of the hardware architecture.⁴⁷ Gains are also possible through new algorithms with lower-levels of computation, as well as through hardware streamlining that implements functions with fewer transistors and less chip area. While there are currently two basic forms of chips, CPUs (central processing units, the logic chip) and GPUs (graphics processing units, applicable to computer graphics and AI uses), more domain-specific, specialized chips could well evolve, bringing performance gains to specific application areas.

Initiating a Broad Post-Complementary Metal-Oxide-Semiconductor Research and Development Effort

While NIST’s NSTC, and to some extent DoD’s ME Commons, may include research on some of these areas, a systematic effort is needed to accelerate research on post-CMOS technologies and approaches that meet commercial and DoD needs, working with NSTC and NIST. (See Recommendations 5.2 and 5.3.)

OVERCOMING REGULATORY BARRIERS

DoD faces a series of barriers from internal security requirements that affect its ability to rapidly adopt advanced chips.

To regulate the security of its platforms and systems, DoD in 2004 developed a “trusted foundry” program initially with IBM and subsequently with other companies for assured, secure manufacturing at U.S. plants of the chips it requires.⁴⁸ The goal of this program was to ensure that DoD understood and controlled the provenance of all custom microelectronics it was procuring. The program reaches integrated circuit design, aggregation, mask making, foundry, and packaging steps to try to assure a “chain of custody” for both classified and unclassified integrated circuits. For example, DoD announced a $3.1 billion 10-year agreement with GlobalFoundries to meet semiconductor needs through the trusted access program.

___________________

⁴⁶ Semiconductor Research Corporation (SRC), 2024, “Nanoelectronics Research Initiative (NRI),” https://www.src.org/program/nri; A. Chen, 2016, “An Overview of Nanoelectronics Research Initiative (NRI),” Paper presented at the 2016 13th IEEE International Conference on Solid-State and Integrated Circuit Technology, ICSICT 2016 – Proceedings.

⁴⁷ C.E. Leiserson et al., 2020, “There’s Plenty of Room at the Top: What Will Drive Computer Performance After Moore’s Law?” Science, June 5, https://www.microsoft.com/en-us/research/uploads/prod/2020/11/Leiserson-et-al-theres-plenty-of-room-at-the-top.pdf.

⁴⁸ Defense Microelectronics Activity (DMEA), 2024, “DMEA Trusted IC Program,” https://www.dmea.osd.mil/TrustedIC.aspx.

GlobalFoundries has dropped out of the race to produce the most advanced chips, however, producing chips at or above the 12 nm scale.⁴⁹ Because semiconductors are pervasive in DoD’s equipment, as noted in Chapter 2, the great majority of the semiconductors embedded in DoD systems are commercial-off-the-shelf components. Only a small minority are customized chips to meet specific DoD functionality, performance, or security requirements. While DoD’s trusted suppliers potentially could meet the latter need, the system does not embrace the most advanced chips, and only 2 percent of DoD’s chips are from that trusted supply chain system.⁵⁰

This has resulted in challenging economics for trusted foundry participants: companies that become “trusted” undergo significant effort to align their business with DoD requirements, and frequently the volume of DoD trusted foundry purchases cannot generate the return on investment these firms need to remain suppliers to DoD’s Trusted Foundry program. The Trusted Foundry program offers a limited suite of microelectronics for DoD systems when evaluated by technology and node.⁵¹ Although the Trusted Foundry program has roughly 80 facilities accredited, only 16 of these facilities are fab lines.⁵² Of these fab lines, many are sole-source suppliers. In addition, access to GlobalFoundries’s 12 nm fab line noted above (the most advanced in the trusted foundry ecosystem), which was recently accredited,⁵³ to date has been quite limited for wafer production runs and untested wafers.⁵⁴

Given these ongoing challenges, in May 2020, the director of defense research and engineering for modernization within the Office of the Under Secretary of Defense for Research and Engineering (OUSD R&E) stated that the current

___________________

⁴⁹ K. Tarsov, 2023, “How GlobalFoundries Aims to Remain World’s Third Biggest Semiconductor Foundry,” CNBC, October 1, https://www.cnbc.com/2023/10/01/how-globalfoundries-aims-to-remain-worlds-third-biggest-chip-foundry.html. Of course, there is a strategic aspect to legacy chips as well as leading-edge chips, because many industries, such as automotive, as well as DoD systems, rely on them. See S. Shivakumar, C. Wessner, and T. Howell, 2023, “The Strategic Importance of Legacy Chips,” Center for Strategic and International Studies, March 3, https://www.csis.org/analysis/strategic-importance-legacy-chips.

⁵⁰ J.M. Donnelly, 2021, “Pentagon Races to Shore Up Supply Chain Security,” Government Technology, April 9, https://www.govtech.com/security/pentagon-races-to-shore-up-supply-chain-security.html.

⁵¹ DMEA, 2024, “Defense Microelectronics Activity (DMEA): TAPO—Foundry Services,” https://www.dmea.osd.mil/TAPOFoundry.aspx.

⁵² DoD, 2023, “Accredited Suppliers,” Trusted Foundry Program, Defense Microelectronics Activity, September 7, https://www.dmea.osd.mil/otherdocs/AccreditedSuppliers.pdf.

⁵³ GlobalFoundries, 2023, “GlobalFoundries and U.S. Department of Defense Showcase Secure Chip Manufacturing at 2023 Trusted Foundry Training,” October 12, https://gf.com/gf-press-release/globalfoundries-and-u-s-department-of-defense-showcase-secure-chip-manufacturing-at-2023-trusted-foundry-training.

⁵⁴ DMEA, 2024, “Defense Microelectronics Activity (DMEA): TAPO—Foundry Services.”

method for acquiring custom microelectronics from a trusted supplier (trusted foundry) system had failed.⁵⁵ The director further stated that to access state-of-the-art (SOTA) microelectronics, DoD needed to move to an evidence-based assurance method that can leverage commercial industry while maintaining hardware security (like Microelectronics Quantifiable Assurance [MQA], discussed below).⁵⁶

The trusted foundry system is part of the Defense Microelectronics Activity (DMEA), a regulatory and testing entity with some 200 staff based in McLellan, California. It manages the trusted access program; the advanced technology support program for microelectronics acquisition and oversight; an engineering program for developing microelectronics solutions, including for legacy systems; and radiation testing for delivering radiation-hardened and tested microelectronics.⁵⁷ DMEA also manages its own foundry, known as the Advanced Reconfigurable Manufacturing for Semiconductors (ARMS) facility.⁵⁸

The regulatory underpinnings for this system run through the International Traffic in Arms Regulations (ITAR) and Export Administration Regulations (EAR), which regulate the export of defense-related technologies, information, and services, including information conveyed to (and therefore work performed by) nonpermanent residents.⁵⁹ The Directorate of Defense Trade Controls in the Department of State leads ITAR, and the Bureau of Industry and Security in DOC leads EAR. ITAR regulates semiconductors and related equipment and materials used in military and space applications, and EAR regulates devices that are dual-use and can be used in either civilian or defense applications. Although much of the talent base for semiconductor R&D is foreign-born, ITAR limits their involvement in government-supported R&D or work, affecting the ability to bring the best talent

___________________

⁵⁵ DoD Inspector General, 2022, “Evaluation of the Department of Defense’s Transition from a Trusted Foundry Model to a Quantifiable Assurance Method for Procuring Custom Microelectronics (DODIG-2022-084),” May 4, https://www.dodig.mil/reports.html/Article/3019461/evaluation-of-the-department-of-defenses-transition-from-a-trusted-foundry-mode.

⁵⁶ Ibid. See also Air Force, 2023, “AA2023 Mandated Independent Review of Microelectronics Quantifiable Assurance,” August 3, https://www.af.mil/Portals/1/documents/2023SAF/MQA_Report.pdf.

⁵⁷ DMEA, 2024, “General Information,” https://www.dau.edu/acquipedia-article/defense-microelectronics-activity-dmea.

⁵⁸ A March 2020 DoD Inspector General report found that DMEA spent $32.4 million between January 2014 and July 2019 to maintain the ARMS foundry while only using it to provide five wafer lots for five DoD customer requests, calling into question its utility and return on investment. But $30 million may be a modest price tag if it enables an important legacy platform to continue to operate. DoD Inspector General, 2020, “Audit of DoD Hotline Allegations Concerning the Defense Microelectronics Activity (DODIG-2020-072),” March 26, https://www.dodig.mil/reports.html/Article/2126034/audit-of-dod-hotline-allegations-concerning-the-defense-microelectronics-activi.

⁵⁹ Code of Federal Regulations (CFR), Title 22, Chapter 1, Subchapter M, Part 120, https://www.ecfr.gov/current/title-22/chapter-I/subchapter-M.

to work on critical advances. A 2020 study found that 40 percent of high-skilled semiconductor workers in the United States were born abroad.⁶⁰ These regulations involve two additional agencies, creating additional incremental delays in serving DoD’s needs for chips. (See Recommendation 5.10.)

The inefficiency of the current system for securing custom advanced chips exacts a significant toll on national security readiness. The recent experience of the Air Force in developing a new jam-resistant Global Positioning System (GPS) capability, a vital defense strategy as the recent war in Ukraine illustrates, was a billion-dollar project, and the needed ASIC chip was designed in a short amount of time. However, it took years of maneuvering through administrative barriers justifying utilization of U.S. facilities at one of the two U.S. suppliers, GlobalFoundries or Intel, which were not even fabricating the most advanced chips available globally. If DoD is effectively blocked by administrative barriers from timely access to advanced chips, then the national security justification behind the CHIPS Act is undermined. It will be important for future procurements of advanced chip designs to benefit from this experience through streamlined procedures that enable much faster adoption.

To utilize the most advanced chips for its custom needs, DoD increasingly must rely on and embrace commercial electronics supply chains. This is at odds with DoD’s traditional approach to security, which historically emphasized cradle-to-grave production in the continental United States, export controls on technology, security through obscurity,⁶¹ and numerous military standards (which often differ substantially from commercial practices) for interfaces, design, manufacturing, standards and testing of electronic devices, and the associated manufacturing processes. Of course, numerous exceptions have been authorized to permit DoD to meet its needs, but significant restrictions on design and manufacturing preferences for custom chips remain. DoD’s continuing restrictions place it at odds with practices in the commercial microelectronics industry, which is inherently global, collaborative, strongly committed to a set of commercial standards, and focused on low-mix, high-volume manufacturing. DoD faces a trade-off: it cannot secure access to today’s leading-edge microelectronics without altering its system for how it manages a secure supply chain. The more closely DoD can align with the

___________________

⁶⁰ W. Hunt and R. Zwetsloot, 2020, “The Chipmakers. U.S. Strengths and Priorities for the High End Semiconductor Workforce,” Center for Security and Emerging Technology (CSET), Georgetown University, September, https://cset.georgetown.edu/publication/the-chipmakers-u-s-strengths-and-priorities-for-the-high-end-semiconductor-workforce.

⁶¹ Security through obscurity, or STO, is the belief that any system can be secure provided no one outside of its development group is allowed to be aware of its internal mechanisms.

commercial supply chain, commercial industry, and commercial standards, the better its access to SOTA microelectronics capabilities will become.⁶²

In light of this problem, the Chief Scientist of the Air Force in 2023 led an independent study with 27 experts to study DoD’s trusted foundries and “quantifiable assurance” approaches to microelectronics security.⁶³ The study found that a new system, MQA, can be used in the future in concert with the trusted foundries system to meet DoD’s mix of needs for classified, unclassified, and export-controlled microelectronics. RAMP and RAMP-C, cited above, represent steps in this direction. MQA is a proposed system to assure confidentiality, integrity, and availability of microelectronics—with access being the overarching requirement. Because of the costs and ever-advancing technology, DoD cannot maintain its own dedicated facilities and relies on the commercial supply chain to meet the great bulk of its needs. Because the commercial chip industry must meet very-high-quality and performance standards and already collects the needed data to enable this, MQA would be a system for independent, data-centric checks on commercial process.⁶⁴

However, a DoD Inspector General report from May 2022 indicates that the transition from a trusted foundry model to an evidence-based assurance alternative approach is “behind schedule” and attributes these delays to “difficulties in developing and staffing new processes” (coronavirus disease 2019 [SARS-CoV-2]), and turnover of key personnel.⁶⁵ In practice, this means that DoD is now 3 years behind the Section 224 requirements of the FY 2020 NDAA, which stipulated that DoD was required to establish trusted supply chain and operational security standards by January 2021 and that DoD purchases of microelectronics meet these standards effective January 2023. (See Recommendations 5.8, 5.9, and 5.15.)

___________________

⁶² Recognition of the importance of more closely aligning DoD standards to the extent possible with commercial standards was conveyed at the 2023 Microelectronics Reliability and Qualification Workshop. See C. Rink, DoD OUSD S&T, 2023, “Microelectronics Policy, Standards and Guidance,” presentation, January 23, https://csrc.nist.gov/presentations/2023/microelectronics-policy-standards-and-guidance.

⁶³ Department of the Air Force, Office of the Chief Scientist and NDAA, 2023, “Mandated Independent Review of USD (R&E) Microelectronics Quantifiable Assurance Effort,” August 3, https://www.af.mil/Portals/1/documents/2023SAF/MQA_Report.pdf.

⁶⁴ Regarding how a testing and auditing system can operate in a related area, see Dario Amodei, CEO Anthropic, “Testimony to the Senate Judiciary Committee, Subcommittee on Privacy, Technology and the Law,” July 25, 2023, https://www.judiciary.senate.gov/imo/media/doc/2023-07-26_-_testimony_-_amodei.pdf.

⁶⁵ DoD Inspector General, 2022, “Evaluation of the Department of Defense’s Transition from a Trusted Foundry Model to a Quantifiable Assurance Method for Procuring Custom Microelectronics (DODIG-2022-084).”

IMMIGRATION

In addition, as will be discussed further in Chapter 7 on workforce education, the immigration system limits the ability to access and retain outstanding foreign science and engineering talent trained in semiconductor fields. As noted above, a recent study showed 40 percent of high-skilled semiconductor workers in the United States were born abroad. This situation calls out for improvement.⁶⁶ Overall, legislation is needed to revise the immigration laws to reflect the reality of technology needs, including that country of origin should not matter when immigrants are selected based on their skills and education, and to enable an accelerated path to citizenship. Meanwhile, without such comprehensive reform, an intermediate step is to award lawful permanent resident status for those with advanced science, technology, engineering, and mathematics (STEM) degrees under current law outside of country or worldwide numerical caps for individuals working in semiconductor fields (and other advanced technology areas). DoD could prioritize such approaches. (See Recommendation 7.2.)

OVERCOMING BARRIERS TO MODERNIZATION

The time it takes for DoD to field new platforms is a significant and growing problem⁶⁷—a new weapons system can take a decade and a half or more to develop. This means that the platforms’ information systems must be updated during development, increasing cost and delay problems. A new ship, aircraft, or tank will often operate for decades, which means its information systems require periodic updating to avoid becoming obsolete. As new electronics technologies evolve, they need to be embedded in existing platforms; yet Congress, in providing defense funding, has historically favored new procurements over modernization. The Defense Innovation Unit (DIU) was formed in 2016 to try to improve the time required for fielding AI, machine learning, autonomy, cyber, and energy savings technologies, largely through trying to rapidly leverage commercial technologies.⁶⁸ Cutting-edge advances in design, as recommended above, could be a significant enabler of DoD semiconductor modernization.

There is another consideration, as well. If China floods the market with legacy semiconductor chips, which it is now producing in growing volumes, then DoD faces a significant set of security issues because of its reliance on legacy chips in

___________________

⁶⁶ PCAST, 2022, “Report to the President on Revitalizing the Semiconductor Ecosystem,” September.

⁶⁷ A. Seraphin, 2023, “Defense Department Semiconductor Concerns,” Presentation to National Defense Industries Association, September 12.

⁶⁸ D. Vergun, 2023, “DoD Modernization Relies on Rapidly Leveraging Commercial Technology,” DoD News, January 25, https://www.defense.gov/News/News-Stories/Article/Article/3277453/dod-modernization-relies-on-rapidly-leveraging-commercial-technology.

its many systems, providing an additional reason for reconsidering DoD’s current modernization approaches. While DoD has a software modernization strategy,⁶⁹ a corresponding strategy for semiconductor hardware updates to improve system performance is needed. (See Recommendation 5.16.)

OVERCOMING WORKFORCE EDUCATION BARRIERS

There are problems noted above in the education systems affecting semiconductors at professional (engineers and scientists) and technical workforce levels, and DoD has long had programs in both areas. The National Science Foundation (NSF) and DOC have responsibilities under the CHIPS Act to form new workforce programs to address semiconductor needs. DoD needs to collaborate with NSF and DOC on these efforts and bring its own workforce education programs to bear. Chapter 7 of this report provides a detailed summary of workforce issues both for the semiconductor industry and DoD and corresponding recommendations.

All of the steps listed above could be considered by DoD as part of a coherent, DoD-wide general semiconductor strategy that it will need to develop to meet its semiconductor needs. Specific recommendations for the barriers discussed in this chapter are referenced above and contained in subsequent chapters. But the need for an overall DoD strategy and unified approach remains.

___________________

⁶⁹ DoD, 2021, “Department of Defense Software Modernization Strategy, Version 1.0,” November, https://media.defense.gov/2022/Feb/03/2002932833/-1/-1/1/DEPARTMENT-OF-DEFENSE-SOFTWARE-MODERNIZATION-STRATEGY.PDF.