4


The Role of Public–Private Partnerships in Supporting Semiconductor Manufacturing

The committee was asked to review and evaluate how public–private partnerships (PPPs) can strengthen semiconductor manufacturing, explore how PPPs can be tailored to address different aspects of the semiconductor supply chain, and explore the merits of establishing a semiconductor manufacturing corporation.

The committee finds that PPPs have a mixed record in strengthening semiconductor manufacturing. There has been substantial research looking into this question, some of which has been funded by the Department of Defense (DoD), as discussed below. Taken together, this research suggests that PPPs can accelerate innovation in low technology readiness level (TRL) basic research that supports semiconductor manufacturing and facilitate mid-TRL applied research that accelerates technology development with an eye toward transition to product manufacturing. To succeed, PPPs must be substantive and have a well-articulated research agenda and goals, robust participation from industry, strong intellectual property (IP) protections, and consistent funding for multiyear periods. PPPs that lack one or more of these characteristics frequently fail to achieve their aims. It is not possible to create a one-size-fits-all PPP that can address the myriad economic and technical challenges facing the semiconductor industry, or address challenges in multiple parts of the semiconductor supply chain simultaneously. In general, PPP objectives must be clear, their scope must be manageable, and their participants and staff constantly engaged and supported. PPPs also need upstream and downstream interactions, as well as to know where they fit in the strategic vision and how to contribute to it.

This research leads the committee to conclude that a PPP can strengthen semiconductor manufacturing provided it has the following characteristics:

• It is well funded.
• It is funded at stable levels for 5–10 years, with annual reviews.
• It is focused on one TRL range, for example TRL 4–6 (the so-called “valley of death”).
• It is focused on a specific supply chain sub-segment.
• It is structured to maximize the possibility of technology transfer to industry.
• It is not restricted solely to U.S. entity membership.
• Its research and IP (and eventually, product sales) can be shared internationally.

The committee does not find that establishment of a semiconductor manufacturing corporation that is a government-owned or government-operated captive fabrication facility (fab) and that exists solely to support DoD microelectronics needs is advisable. For the techno-economic reasons discussed in previous chapters, a DoD-centric semiconductor manufacturing corporation is highly unlikely to deliver the variety of mature and leading-edge semiconductors DoD requires at commercially competitive timelines and prices.

On the other hand, a public–private semiconductor manufacturing corporation that serves primarily as the administrative coordinator of DoD, other government, and private subsidies for commercially oriented, next-generation fabrication technology development and capacity expansion might be a concept worth exploring. That model would be analogous to the highly successful Semiconductor Research Corporation (SRC) public–private semiconductor research and development (R&D) partnership, but focused on nearer-term semiconductor design, fabrication, and deployment for technology nodes beyond those currently deployed.

With or without such a PPP, DoD will be well served by making every effort to ensure that leading-edge chip manufacturers are successful in increasing U.S.-based production that is commercially successful and viable and by being an engaged partner with these firms. This section focuses on how PPPs can support semiconductor manufacturing more generally and potentially address DoD-specific supply chain challenges.

DoD commissioned studies analyzing the role of PPPs in the microelectronics industry in 2017,¹ 2021,² and now 2023 (for this committee’s work). These studies emphasize shared characteristics and themes of successful PPPs, which can inform

___________________

¹ Potomac Institute for Policy Studies, 2017, “Consortia Analysis and Recommendations Trade Study,” https://www.potomacinstitute.org/reports/43-pips-reports/191-consortia-analysis-and-recommendations-trade-study.

² V. Pena, M.M.G. Slusarczuk, J. Mandelbaum, et al., 2021, “Lessons Learned from Public-Private Partnerships (PPPs) and Options to Establish a New Microelectronics PPP,” IDA Document: D-22782, https://apps.dtic.mil/sti/trecms/pdf/AD1200224.pdf.

a model PPP to address one or more aspects of DoD’s microelectronics challenges. Before proceeding with findings and recommendations in response to the second item in the statement of task (“How can public–private partnerships strengthen semiconductor manufacturing?”), the findings of these reports merit review.

POTOMAC INSTITUTE: CONSORTIA ANALYSIS AND RECOMMENDATIONS TRADE STUDY

In 2017, the Potomac Institute for Policy Studies conducted a 6-month study to identify lessons learned from the history of semiconductor R&D consortia and government R&D efforts involving technology transition, and to apply these to the current needs of the semiconductor industry. The study examined six different semiconductor PPPs, with a focus on identifying organizations in the mid-range TRLs (4–7). Case studies were developed on the Very High-Speed Integrated Circuits Program (VHSIC), the Semiconductor Manufacturing Technology Consortium (SEMATECH), Manufacturing USA, the Industrial Technology Research Institute (ITRI, in Taiwan), the Interuniversity Microelectronics Centre (IMEC, in Belgium), and the Faraday Centers (in the United Kingdom). This study made five recommendations based on its findings:

• Funding: Ensure that the funding level of any major public–private R&D initiative is at a magnitude that mirrors previous successful initiatives: $200–$300 million per year, 10-year timeline, total budget of $2 billion–$3 billion, in 2017 figures.
• Technology transition: Include costs for technology transition and insertion in the budget.
• Major industry role: Follow industry’s lead while making sure the U.S. government still benefits. Ensure cost sharing to the extent feasible between government and industry.
• Focus on low volume: Focus public–private R&D efforts on low-volume, customizable manufacturing solutions to technical challenges.
• Procurement vehicles: Use Other Transaction Authority (OTA) acquisition mechanisms in all R&D programs.

INSTITUTE FOR DEFENSE ANALYSES: LESSONS LEARNED FROM PUBLIC–PRIVATE PARTNERSHIPS AND OPTIONS TO ESTABLISH A NEW MICROELECTRONICS PUBLIC–PRIVATE PARTNERSHIP

In 2021, the Defense Advanced Research Projects Agency (DARPA) funded the Institute for Defense Analyses to study and analyze prior and ongoing PPPs to inform objectives for a new PPP that could advance microelectronics R&D, potentially by

supporting infrastructure to meet prototyping needs across the industry. This study surveyed a variety of PPPs, assessing their ability (or lack thereof) to achieve their stated goals. This study identified 32 lessons learned, several of which are particularly relevant to the exploration of how PPPs can strengthen semiconductor manufacturing.

• Goals: The goals of the PPP must be clearly defined and different visions on topics ranging from basic research, proof of concept testing, prototyping, and workforce development must be reconciled.
• Governance: A critical decision is the choice of governance model. Models observed ranged from consultative decision-making by executive leaders to consensus voting by members. The critical factor for success is that the governance is transparent and has the broad confidence and support of the PPP members. The realm of governance must include the high-level business strategy, the technical agenda and priorities, member engagement, and clearly defined success measures, and it must be consistent with the members’ authorities and business models.
• Funding: The funding structure must be flexible to accommodate varied members’ expectations and sufficient to support the PPP’s mission. Funding structures tied to governance must permit resolution of different opinions to ensure that members do not exit the PPP and allow for a process to attract new partners as the PPP evolves.
• Intellectual property policies: IP policies and rules must be defined up front, and one should anticipate that this will be challenging, given the widely different approaches that exist in industry, university, and government and the need to harmonize them. These policies must adapt to a range of preexisting commitments that prospective members have, their general policy approaches, and their attitudes toward physical security and export control. ITAR control of defense articles presents a significant obstacle for non-U.S. participation.
• Evaluation and measures of success: Measures of success must be tied to the PPP’s goals. These measures may include technical milestones as well as economic and social returns, such as the creation of new businesses, jobs, and social well-being. Financial sustainability, or the degree of self-sufficiency from federal funds, is another success measure. However, the degree and timelines for self-sufficiency may vary depending on the PPP’s goals and the scale of investments, for instance, in new R&D and prototyping infrastructure. The long-term support of the needed operational infrastructure should be considered as part of the PPP’s funding model. In addition, for any PPP that operates on long timelines, ensuring regular evaluations of progress (both quarterly and annually) will inform government and industry participants eager to evaluate the pace and likelihood of breakthroughs.

This committee’s findings align with the findings of these earlier studies. PPPs can strengthen semiconductor manufacturing and support DoD’s needs, directly and indirectly. PPPs can directly strengthen semiconductor manufacturing by convening stakeholders (generally a mix of industry, academia, and government) and enabling and accelerating innovation (TRL 1–3), maturing existing technologies through prototyping (TRL 4–6), or serving as a vehicle to transfer and transition technologies to production (TRL 7–9).³ PPPs can also indirectly strengthen semiconductor manufacturing by serving as a forum to engage unconventional parts of the semiconductor ecosystem, including venture capital, 2- and 4-year colleges and universities, start-ups, and local governments. Engagement with these otherwise disparate parts of the semiconductor ecosystem under the auspices of a PPP can result in knowledge transfer, technology transfer, and workforce training that ultimately supports semiconductor manufacturing.

This chapter proceeds by describing ways that PPPs can directly support semiconductor manufacturing (with examples), ways that PPPs can indirectly support semiconductor manufacturing, and key features of successful PPPs. Related to this chapter, there is a “playbook” in Appendix C that could be followed to establish a PPP that supports semiconductor manufacturing.

PUBLIC–PRIVATE PARTNERSHIPS AND DIRECT SUPPORT TO SEMICONDUCTOR MANUFACTURING

Recalling the findings of earlier studies⁴ on semiconductor PPPs that emphasized the need for clear goals, narrow scoping, and measurable metrics of success, in general, these PPPs should only focus on one range of the lines of effort: TRL 1–3, TRL 4–6, or TRL 7–9. For example, a PPP that attempts to investigate the materials science behind a prospective post-complementary metal-oxide-semiconductor

___________________

³ Technology readiness levels (TRLs) are a type of measurement system used to assess the maturity level of a particular technology. Each technology project is evaluated against the parameters for each technology level and is then assigned a TRL rating based on the project’s progress. There are nine technology readiness levels. TRL 1 is the lowest, and TRL 9 is the highest. For example: TRL 1—When a technology is at TRL 1, scientific research is beginning and those results are being translated into future research and development. TRL 4—Once a proof-of-concept technology is ready, the technology advances to TRL 4. During TRL 4, multiple component pieces are tested with one another. TRL 7—TRL 7 technology requires that the working model or prototype be demonstrated in a relevant environment (in the case of the semiconductor industry, this would be a fab). Also see https://www.nasa.gov/directorates/somd/space-communications-navigation-program/technology-readiness-levels.

⁴ Potomac Institute, 2017, “Consortia Analysis and Recommendations Trade Study (CARTS),” Potomac Institute for Policy Studies, https://usmicroelectronics.mit.edu/wp-content/uploads/2022/06/DARPA-Consortia-analysis-and-recommendations.pdf; Pena et al., 2021, “Lessons Learned from Public-Private Partnerships (PPPs) and Options to Establish a New Microelectronics PPP.”

(post-CMOS) technology while simultaneously developing the prototyping infrastructure to support volume manufacturing of that technology is at high risk of failing to succeed in either endeavor.

Given the scale and expense required to innovate and compete in the semiconductor industry, PPPs must be well-scoped to make progress on a discrete challenge and execute its research agenda in a manner that lends itself to technology transition to industry. Semiconductor PPPs engaged in research that lacks industry interest or commercial appeal will almost certainly fail to generate IP or innovations that meaningfully support semiconductor manufacturing. In general, PPPs can support semiconductor manufacturing by convening a consortium of members to make progress on a research agenda in one or more of the following areas.

Semiconductor Basic Research and Development (TRL 1–3)

PPPs can facilitate high-risk and high-reward foundational R&D into new materials, software tools, and instruction set architectures to establish proof-of-concept applications for semiconductor manufacturing. This research uses analytical and laboratory studies to establish the viability of a speculative technology before it is ready to proceed to the next stage of development. Often, a proof-of-concept may be generated at this stage.⁵ However, it also usually necessary for basic research teams to have a sustained engagement throughout the product development process and the production process, since new scientific questions and technical challenges frequently arise at each stage.

As discussed in Chapter 3, there are a wide variety of post-CMOS materials and devices being explored by the semiconductor industry. A PPP could be established with a research agenda focused on investigating one or more of these post-CMOS materials for DoD and industry microelectronics uses. For example, a PPP focused on basic R&D could explore the suitability of carbon nanotube transistors or graphene field effect transistors as a post-CMOS alternative.^6,7

Semiconductor Applied Research and Development (TRL 4–6)

PPPs can facilitate applied R&D that takes existing proofs-of-concept and validates their utility in a laboratory environment. At this stage, once the basic science of a technology has been established and a proof-of-concept generated, multiple

___________________

⁵ C.G. Manning, 2023, “Technology Readiness Levels,” NASA, September 27, https://www.nasa.gov/directorates/somd/space-communications-navigation-program/technology-readiness-levels.

⁶ B. Ham, 2020. “Carbon Nanotube Transistors Make the Leap from Lab to Factory Floor,” MIT News, June 1, https://news.mit.edu/2020/carbon-nanotube-transistors-factory-0601.

⁷ A.P. Singh, P.N. Shankar, R. Baghel, and S. Tirkey, 2023, “A Review on Graphene Transistors,” 2023 IEEE International Students’ Conference on Electrical, Electronics and Computer Science (SCEECS), https://doi.org/10.1109/SCEECS57921.2023.10062965, pp. 1–6.

component pieces are tested with one another and simulations are run to validate that the technology functions in realistic environments (in this case, a fab). At this stage, a fully functional prototype may be developed.⁸

The Department of Energy (DOE) and three of its national laboratories, in partnership with Intel, Motorola, AMD, and Micron, established a 3-year PPP in the late 1990s to build a proof-of-concept extreme ultraviolet (EUV) lithography tool as part of the industry’s efforts at the time to identify a next-generation lithography method.⁹ This PPP was focused specifically on applied R&D: maturing the technology for use in a commercial high-volume semiconductor manufacturing fab. The result of this PPP was the so-called Engineering Test Stand, a functional prototype EUV tool and the predecessor to today’s EUV tools sold by ASML.

Semiconductor Prototyping Infrastructure (TRL 7–9)

PPPs can create the physical infrastructure necessary for low-volume semiconductor manufacturing (also referred to as “nanofabs”), allowing faster feedback loops between creating a speculative new chip design and determining whether it works as intended. At this stage, prototypes are tested in a fab environment for incorporation into a high-volume semiconductor manufacturing flow and, if successful, the technology is incorporated into a manufacturing process.

For example, the Global450 Consortium (G450C) was established in 2012 (although efforts began as early as 2008) with the goal of developing the systems, process IP, and infrastructure necessary to aid the industry’s then-expected transition from 300 mm wafers to 450 mm wafers (in general, the larger the wafer size, the more favorable the economies of scale).^10,11,12 G450C’s membership consisted of SUNY Albany’s College of Nanoscale Science and Engineering (CNSE), Intel, TSMC, Samsung, IBM, GlobalFoundries, and Nikon.¹³ Although this consortium disbanded in 2017, and the industry has yet to adopt 450 mm wafer manufacturing, this is an example of a PPP that supported semiconductor manufacturing specifically through

___________________

⁸ C.G. Manning, 2023, “Technology Readiness Levels,” NASA, September 27, https://www.nasa.gov/directorates/somd/space-communications-navigation-program/technology-readiness-levels.

⁹ D.D. Sweeney, 1999, “Extreme Ultraviolet Lithography,” Lawrence Livermore National Laboratory, https://www.llnl.gov/sites/www/files/2020-05/euvl-STR-Nov-99.pdf.

¹⁰ P. McLellan, 2022, “Whatever Happened to 450mm Wafers?” Cadence, August 18, https://community.cadence.com/cadence_blogs_8/b/breakfast-bytes/posts/450mm-wafers.

¹¹ Silicon Semiconductor, 2012, “Global Consortium to Make the Move to 450mm,” August 21, https://siliconsemiconductor.net/article/75801/Global_Consortium_To_Make_The_Move_to_450mm.

¹² Intel, 2008, “Intel, Samsun Electronics, TSMC Reach Agreement for 450mm Wafer Manufacturing Transition: Companies Target Common Timeline for 450mm Wafer Pilot Line Readiness,” https://www.intel.com/pressroom/archive/releases/2008/20080505corp.htm.

¹³ J. Hruska, 2017, “450mm Silicon Wafers Aren’t Happening Any Time Soon as Major Consortium Collapses,” ExtremeTech, https://www.extremetech.com/computing/242699-450mm-silicon-wafers-arent-happening-time-soon-major-consortium-collapses.

development of novel prototyping infrastructure.¹⁴ Semiconductor manufacturing customers validated the technical viability and economic appeal of 450 mm wafer manufacturing in fab environments, the relevant tooling and equipment innovations were in place, and infrastructure required to support the transition from 300 mm to 450 mm manufacturing was characterized.

Semiconductor Supply Chain

PPPs can pursue basic or applied research with the explicit goal of testing new materials, design tools, or equipment and resolve a known supply chain choke point. For example, the semiconductor industry’s consumption of hydro-fluorocarbons (HFCs), a greenhouse gas for which use is increasingly restricted internationally under the Kigali Amendment to the Montreal Protocol, necessitates that the industry develops one or more alternatives. HFCs are used by the semiconductor industry throughout the manufacturing process and are highly valued for their levels of purity. Ideally, an alternative will be developed by industry for industry, but there is a first mover problem in that no one firm has the resources to solve this challenge. A PPP could address this first mover problem and develop a standardized set of alternatives to HFCs to support semiconductor manufacturing through the formation of a consortia of members, innovating around this known choke point and limiting the industry’s use of this environmentally hazardous material.^15,16,17

PUBLIC–PRIVATE PARTNERSHIPS AND INDIRECT SUPPORT TO SEMICONDUCTOR MANUFACTURING

PPPs can also strengthen semiconductor manufacturing indirectly, acting as a convening forum to accelerate innovation in each of the areas above and serve as a source of training and knowledge diffusion. By convening a broad

___________________

¹⁴ S. Jones, 2022, “The Lost Opportunity for 450mm,” SemiWiki [blog], April 15, https://semiwiki.com/semiconductor-services/techinsights/311026-the-lost-opportunity-for-450mm.

¹⁵ Environmental Protection Agency, 2021, “Market Characterization of the U.S. Semiconductor Industry,” https://www.epa.gov/sites/default/files/2021-03/documents/epa-hq-oar-2021-0044-0002_attachment_3-semiconductors.pdf.

¹⁶ Semiconductor Industry Association (SIA), 2021, “Comments of the Semiconductor Industry Association (SIA) on the Notice of Proposed Rulemaking: Phasedown of Hydrofluorocarbons: Establishing the Allowance Allocation and Trading Program Under the American Innovation and Manufacturing Act,” https://www.semiconductors.org/wp-content/uploads/2021/07/SIA-comments-on-EPA-HFC-Phasedown-Rule-july-2-2021.pdf.

¹⁷ Department of State, 2023, “The Montreal Protocol on Substances That Deplete the Ozone Layer,” https://www.state.gov/key-topics-office-of-environmental-quality-and-transboundary-issues/the-montreal-protocol-on-substances-that-deplete-the-ozone-layer.

membership that includes some of the entities listed below, PPPs can facilitate technology transfer to industry. PPPs with diverse membership and partnerships enjoy a variety of advantages, each of which indirectly can support semiconductor manufacturing.

• Local and state governments: Local and state governments have the ability to provide direct economic incentives (subsidies) as well as indirect incentives (regulatory facilitation and permitting) that can increase the speed and ease of PPP operations.
• Start-ups and small businesses: PPPs that explicitly include small and medium-sized businesses (in addition to established players) act as a convening forum whereby new firms can better understand their prospective customer or business partner priorities, increasing the changes of long-term success for the smaller entities. These small businesses and start-ups also gain exposure through their participation in PPPs insofar as larger established firms get to see novel approaches to industry challenges.
• Venture capital: PPPs can attract venture capital firms and ensure that innovations derived from the work of the PPP have a path to commercialization with private capital support (whether from corporate or commercial venture capital).
• Colleges and universities: PPPs can convene students, postgraduates, industry experts, and potentially federal laboratory employees in a forum that facilitates knowledge sharing and learning by doing.
• Workforce: PPPs, through their work with colleges and universities in particular, can serve to increase the number of trained workers that support the semiconductor industry. This opportunity is described in Chapter 7, where workforce issues more generally are discussed.
• Information sharing: PPPs can also support semiconductor manufacturing by serving as an information-sharing service. For example, PPPs can make the findings of their work entirely public, and by sharing important technical data broadly with industry, these findings can inform related research efforts that are happening elsewhere but not necessarily under the auspices of the PPP itself.

KEY FEATURES OF SUCCESSFUL PUBLIC–PRIVATE PARTNERSHIPS

Successful PPPs are easy to work with and for; have a clear value proposition that appeals to industry, academic, and government participants; and transparent operational structure that ensures all participants derive equitable benefit from the PPP’s work. Successful PPPs that make genuine advances in semiconductor manufacturing must be funded with large and patient capital, given the long timelines

necessary to innovate in the semiconductor industry. In practice, this means that a PPP needs to be clear about its research agenda from the start, have well-defined metrics for success, and clear IP provisions. A PPP with these features will appeal to the semiconductor industry, whose participation is essential. Importantly, participation from industry also may allow for easier and faster access to physical facilities that are not otherwise available.

This section describes each of these features in greater detail, concluding with examples of PPPs that focus on different scopes of work and the various features necessary to ensure their success. See Box 4-1 for a PPP case study.

Scope and Clarity of Goals

A semiconductor PPP cannot and should not endeavor to solve broad problems facing this industry (e.g., “invent the future”). While such efforts are necessary, they are more appropriately directed by entities with skill in managing complex R&D agendas (such as DARPA). In general, PPPs are not optimal for basic R&D work that supports semiconductor manufacturing. Instead, PPPs are instead better positioned to address TRL 4–6 problems, as recognized by DoD’s 2023 Microelectronics Commons (ME Commons) effort. Cost sharing will always vary based on the level of risk in a PPP’s scope. Thus, TRL 1–3 tasks indicate higher risk, and thus one expects higher government investment, whereas TRL 4–6 or 7–9 tasks indicate somewhat lower risk and more balanced investment between government and industry. The scale of resources required to address most of the current concerns in the semiconductor sector, from workforce to capital, is simply too large for any one PPP to make broad progress on an industry-relevant timeline. Rather, individual semiconductor PPPs should address discrete challenges (i.e., as demonstrated by earlier PPPs that sought to “mature EUV technology for use in a fab” and “develop a pre-competitive 450 mm wafer prototyping fab facility”) with a clear vision of success and transition to industry for commercialization.

Well-scoped PPPs focus on a narrow band of TRL and a well-defined semiconductor supply chain sub-segment. For example, a PPP focused on enabling early-stage R&D (TRL 1–3) and prototyping (TRL 4–6) of, say, new electronic design automation (EDA) tools will necessarily have a different structure, goals, governance, funding, and participation than a PPP focused on maturing a specific semiconductor manufacturing process technology in preparation for its inclusion in high-volume manufacturing (TRL 7–9). Likewise, a PPP that aims to advance breakthroughs in upstream basic research in novel semiconducting materials (such as graphene or carbon nanotubes) is not well suited to simultaneously conduct downstream applied research on EDA tools.

Metrics for Success

In tandem with these clear goals and scope, a PPP should have a vision for success and metrics to evaluate progress. These metrics could consist of statistics, including (1) the total number of partners (industry and government agencies or entities), (2) the number of patents or copyrights filed and licensed within 10 years of program’s start, and (3) the number of products, especially products acquired by the government that contain IP resulting from the collaborative work, as identified by performers and transition partners, or (4) the level of follow-on investment from non-government PPP members.

Intellectual Property

In general, IP treatment in a PPP should be determined collaboratively, ideally by an advisory council consisting of PPP participants who define mutually agreeable terms and conditions. There is no one-size-fits-all approach to IP treatment among semiconductor industry PPPs. Regardless of the particular part of the semiconductor supply chain being targeted by a given PPP, IP protections will have to follow one of three general options:

• Public. The results and findings from a PPP are shared with the public on an open-source or open-access basis.
• PPP members only. The results and findings from a PPP are shared with PPP members only. This model can offer members either an exclusive royalty-free license or a first-right-of-refusal opportunity to license the technology developed in the PPP.
• PPP R&D performers only. The most restrictive approach to PPP IP handling—the results and findings from a PPP are shared with only the subset of PPP members who perform the R&D.

In addition to these options, PPPs that make use of federal government R&D funds must also consider several important laws that afford the government special rights to the IP. These include the following:

• Government purpose rights. The government retains the right to use any breakthroughs a PPP may accomplish in associated government efforts.
• March-in rights. If the IP generated by a PPP is not being adequately commercialized, the U.S. government retains the right to make the patent(s) and license(s) available.

The treatment of IP in PPPs is addressed in greater detail in Chapter 5 in the section “Addressing Bureaucratic and Regulatory Barriers.”

Timeline and Funding

PPPs need to be given adequate time and funding to succeed. PPPs need 6–12 months to solicit initial membership interest and funding. During this “phase 1” period, the scope of the work can be determined. In general, advances in TRL 1–3 or TRL 4–6 are possible within a period of 3–5 years. However, substantive advances in applied research, especially in semiconductor manufacturing and semiconductor manufacturing equipment, will likely require additional time.

PPPs require considerable funding to generate advances that will meaningfully address one or more of the challenges facing the semiconductor industry. The ratio of funds from government versus industry should depend on the level of risk associated with the PPPs research agenda: high-risk research requires greater government funding. Government funding is essential for semiconductor PPPs because it provides “patient” and consistent support to stabilize the PPP against the risk that one or more industry partners might cease funding for one reason or another. For example, IMEC reports that approximately 75 percent of its annual operations are funded by semiconductor industry participants, while 25 percent of its operating funds come from a variety of government funding sources.¹⁸ The fraction of government funding was much larger in the early years after IMEC’s founding, as appropriate for an entity that was working to establish a new model for global R&D.

Physical Facilities

A semiconductor PPP needs access to facilities and equipment, as well as technical and administrative staff. Ideally a preexisting facility can be leveraged (to maximize the speed with which a PPP begins operations), but importantly, this facility should be independent and not onsite at a single government or industry participant location. The larger of the PPP participants should be expected to contribute technical staff to this new facility, increasing their commitment, limiting freeriding, and maximizing engagement. As an alternative approach, participants may choose to develop technology in their respective facilities pursuant to an IP agreement to collaborate at the pre-patent and pre-commercial stage. This arrangement has the benefit of allowing each partner to control their IP development internally while still being obligated to share it with select partners. Importantly, however, this model only works well if the companies are not competitors (e.g., if participant companies support different parts of the supply chain).

___________________

¹⁸ Potomac Institute, 2017, “Consortia Analysis and Recommendations Trade Study,” Potomac Institute for Policy Studies, https://potomacinstitute.org/images/studies/CARTSsm.pdf.

Public–Private Partnership Membership and Industry Alignment

A semiconductor PPP should be led and funded primarily by industry; however, the specific levels of participation or funding vary commensurate with level of risk of the PPP’s research agenda. Maximizing industry leadership, engagement, and participation is the single most important factor when ensuring a PPP supports a manufacturing objective. Crafting a structure that incentivizes industry to contribute technical staff to collaborate in a precompetitive forum is ideal.

Different PPP projects will inevitably have varying levels of industry participation depending on how short or long term the project is and whether the project involves basic or applied R&D. For example, a PPP focused on TRL 1–3 will likely see its research agenda reflect the priorities of universities and government laboratories that focus much of their work at this TRL level, while a PPP focused on TRL 7–9 will have a research agenda much more tailored to the commercial partners eager to transition the innovation to high-volume manufacturing. Also, industry involvement will be affected by the nature of the projects the PPP pursues. For example, as the 5-year timetable for the government funding for the Manufacturing USA Institutes ramped down, only large firms were able to provide support for continuing the institutes. However, these larger firms could not justify investments in projects that would not directly benefit them, such as for SMEs, or projects that trained workforces other than their own.

Well-scoped PPPs ensure that their membership and industry alignment reflects the type of R&D the organization will engage in, the consolidation present in that particular sub-segment of the supply chain, and the level of capital required for the PPP to realize its desired goals. For example, a semiconductor sector PPP that hopes to make meaningful innovations in the field of photoresists will likely have to include membership from prospective customers (fabrication plants, or “fabs”), equipment vendors that make use of this photoresist, established photoresist manufacturers, and academic experts in the field. While this PPP will require substantial capital, photoresist manufacturing advances do not necessitate access to a high-volume fab at the prototyping stage, meaning that capital costs for the PPP will be relatively low. In contrast, a PPP that is focused on facilitating advances in semiconductor lithography will require participation from established industry leaders (both suppliers and customers of current lithography tools) and the substantial capital required to make progress in this high-cost segment of the tooling supply chain.

For PPPs that focus on early-stage research and development or prototyping, PPP membership should consist of organizations that excel at basic R&D. In practice, basic R&D in the United States is most frequently carried out by federally funded research and development centers (FFRDCs) and academia. As such, a PPP focused on early-stage research would have membership that consists of representatives from these fields and governance that reflects those

priorities. PPPs focused on early-stage R&D are also at the stage where the government can exert the most influence over the direction and outcomes of a PPP’s research program. PPPs focused on early-stage research will involve smaller sums of money and a focus on high-risk, high-reward research that can be crafted to align with government priorities, including those of DoD. In contrast, PPPs focused on later-stage applied research and semiconductor manufacturing will involve much higher capital costs and strong industry representation with an eye toward commercialization.

For PPPs that are focused on later-stage applied R&D as well as technology maturation in anticipation of transition to industry, membership and governance will necessarily focus more on ensuring greater representation from industry. The semiconductor industry is mature and heavily consolidated, which necessitates that PPPs designed to target a particular semiconductor supply chain sub-segment must ensure representation from existing industry players. This representation will ensure that the PPPs’ work is aligned with industry priorities (i.e., in line with concurrent research on the topic happening in standards-setting bodies or other precompetitive forums) as well as offering industry the opportunity to evaluate the PPPs’ work first-hand and assess whether the IP being generated is suitable for license and company use.

Table 4-1 presents examples of how a PPP could be tailored, based on the features described in this section, to address specific semiconductor challenges. Table 4-1 illustrates examples of notional PPPs and does not constitute committee recommendations.

TABLE 4-1 Examples of How a Public–Private Partnership (PPP) Could Strengthen Semiconductor Manufacturing and Address Different Aspects of the Supply Chain

NOTE: AI, artificial intelligence; EDA, electronic design automation; fab, fabrication; R&D, research and development; TRL, technology readiness level.

In light of rapidly evolving chip advances to improve security, size, weight, and performance, it is also important that hardware updates be incorporated effectively and efficiently into older systems on a much more frequent and ongoing basis. Planned updates should be factored into the design process for new systems. DoD’s engagement with PPPs should reflect these points, working in concert with private-sector partners to deploy modern EDA tools, including those that make use of AI, to facilitate and streamline the replacement of older chipsets.

TARGETING PUBLIC–PRIVATE PARTNERSHIPS TO ADDRESS SPECIFIC DEPARTMENT OF DEFENSE EQUITIES IN THE SEMICONDUCTOR SUPPLY CHAIN

The committee was asked to address whether and how a PPP could support semiconductor manufacturing and the associated supply chain, including tool manufacturing, fabless design, electronic design automation, software development, manufacturing capability and capacity, workforce development, domestic research and engineering capture (e.g., hardware start-ups), and raw materials (e.g., wafers, rare earths). This section responds to these prompts by following the manner in which the semiconductor supply chain is organized, beginning with raw materials and concluding with assembly, testing, and packaging. This section focuses on DoD-specific considerations related to each aspect of this supply chain.

In general, the semiconductor supply chain consists of R&D, design, manufacturing, and assembly, testing, and packaging. Within each of these broad segments there are many sub-segments. For example, within “manufacturing,” the supply chain consists of raw and processed materials (e.g., bare wafers and high-purity process gases), photoresist, photomasks, semiconductor manufacturing equipment, and fab infrastructure. Each of these supply chain sub-segments requires different subject-matter expertise, from materials science and chemistry to microscopy and device physics. This section describes DoD equities in each of these areas of the supply chain, emphasizing opportunities where a PPP may increase semiconductor supply chain resilience.

Materials (Chemicals, Gases, and Substrates)

Raw and processed materials are consumed intensively throughout the semiconductor manufacturing process. Roughly two-thirds of all elements in the periodic table have been used in the semiconductor manufacturing process at one time or another.¹⁹ The U.S. Geological Survey, which maintains a list of 35 critical minerals, identifies 30 of these as relevant to semiconductor manufacturing. These critical minerals are not uniquely critical to the semiconductor industry. For example, these minerals may also be critical for the aerospace or large-capacity battery industries.

In addition to these raw elements, specialty materials like high-purity isopropyl alcohol, electronic-grade gases, chemical mechanical planarization slurries, and physical vapor deposition targets are used in semiconductor manufacturing. As a result of this tremendous complexity, firms specialize in the supply of one or more of these sub-markets. Many of these materials are commoditized, meaning there is a relatively small profit margin and whatever profit can be derived from their supply is not sufficient to fund large R&D budgets. Furthermore, because much of the R&D for these commoditized materials is relatively easily copied, firms face a further disincentive to invest in materials innovation research. Adding to these challenges in materials R&D, total consolidated worldwide demand for some of these specialty suppliers only supports one to three firms. As a result, increasing overall supply through subsidies that incentivize U.S.-origin manufacturing is inadvisable and would result in a scenario where oversupply may harm firms and affect availability. For example, funding entirely new photoresist production in the United States could distort the market such that overall availability of photoresist is reduced as profits fall and firms exit the market in the medium to long term.

U.S. firms like DuPont, Brewer Scientific, Photronics, and Entegris are active (and in some cases lead) in select materials sub-markets, while other markets

___________________

¹⁹ N. Draeger, 2019, “Happy 150th Birthday to the Periodic Table,” LAM Research, December 5, https://newsroom.lamresearch.com/Happy-150th-Birthday-to-the-Periodic-Table.

are dominated by firms in Europe and the Asia-Pacific. Notably, Japanese firms maintain a strong position in the supply of photoresists and photomasks as well as the supply of bare wafers, where Taiwanese firms such as GlobalWafers also have significant market share.

DoD is exposed to, and relies on innovation in, the materials that support semiconductor manufacturing. Previous DoD reports have examined its reliance on rare-earth element supply chains as well as raw material supply chains.²⁰ DoD maintains organizations such as the Defense Logistics Agency whose purpose is to ensure a stable supply of national security–critical raw and processed materials.²¹ In addition, DARPA recently convened a workshop focused on novel approaches to rare-earth element separation.²² However, the Defense Logistics Agency and other DoD organizations are not tasked specifically with stockpiling specialty semiconductor materials and upstream products, nor reshoring production of these materials (e.g., through the Defense Production Act). Separately from DoD efforts, DOE is pursuing a variety of initiatives funded via the Bipartisan Infrastructure Law to increase domestic critical mineral and rare-earth element availability, which may have positive indirect effects for DoD supply chain resilience to the extent they reshore U.S. production.²³

___________________

²⁰ DoD, 2022, “Securing Defense-Critical Supply Chains: An Action Plan Developed in Response to President Biden’s Executive Order 14017,” February, https://media.defense.gov/2022/Feb/24/2002944158/-1/-1/1/DOD-EO-14017-REPORT-SECURING-DEFENSE-CRITICAL-SUPPLY-CHAINS.PDF.

²¹ Defense Logistics Agency (DLA), 2024, “DLA Strategic Materials,” https://www.dla.mil/Strategic-Materials.

²² DARPA, 2023, “DARPA Seeks Input on Novel Methods to Separate, Purify Rare Earth Elements,” July 12, https://www.darpa.mil/news-events/2023-07-12.

²³ Department of Energy, 2024, “Rare Earth Security Activities: Office of Manufacturing and Energy Supply Chains,” https://www.energy.gov/mesc/rare-earth-security-activities.

Research and Development

R&D is essential for semiconductor industry leadership. U.S. semiconductor firms lead the world in semiconductor R&D, whether measured by overall firm R&D spending levels ($40 billion in 2019) or R&D spending as a percent of net sales (an average of 18.75 percent in 2023).²⁴ DoD receives roughly $95 billion annually to fund its R&D activities, some of which is directed specifically to semiconductor manufacturing purposes.²⁵

Notably, DoD received $2 billion under the CHIPS Act to support DoD-specific microelectronics research. Separately, DARPA has funded the Electronics Resurgence Initiative (ERI, and now ERI 2.0) and maintains a Microsystems Technology Office (MTO) with a variety of programs focused on inventing the future of microelectronics under the auspices of the Under Secretary of Defense for Research and Engineering.^26,27 The Under Secretary of Defense for Acquisition and Sustainment also manages a wide variety of programs focused on microelectronics R&D.

The most visible example of DoD’s focus on microelectronics R&D was the 2023 establishment of the eight ME Commons hubs. These hubs, which each received initial funding in the tens of millions of dollars, aim to advance a wide

___________________

²⁴ SIA Factbook 2023 (18) and CSET Semiconductor Supply Chain report (12).

²⁵ GAO, 2023, “Research and Development: DOD Benefited from Financial Flexibilities But Could Do More to Maximize Their Use,” GAO-23-105822, June 29, https://www.gao.gov/products/gao-23-105822.

²⁶ OUSD R&E, 2024, “Microelectronics Commons,” https://www.cto.mil/ct/microelectronics/commons.

²⁷ DARPA, 2023, “Electronics Resurgence Initiative 2.0,” March 6, https://www.darpa.mil/work-with-us/electronics-resurgence-initiative.

variety of microelectronics research initiatives relevant to DoD needs.²⁸ This work is happening simultaneously and separately from the work being guided by the DOC and NIST to establish the National Semiconductor Technology Center (NSTC) as well as related initiatives focused on advanced packaging, metrology, and a Manufacturing USA institute.

Electronic Design Automation and Software Development

EDA tools are the backbone of semiconductor design. These tools are essential for creating semiconductor designs, assisting engineers with the task of layout and defect detection. U.S. firms Cadence and Synopsys are dominant in this market, as is Mentor Graphics (now owned by Siemens, Germany). Combined, these three firms account for roughly 75 percent of global market share in EDA tools. These EDA firms are increasingly making use of AI to accelerate design cycle timelines and reduce the overall cost associated with designing a chip.²⁹

Like all other chip customers, DoD relies on EDA tools for the design of custom legacy and leading-edge microelectronics, and in some cases likely uses EDA tools to assist in the integration of commercial-off-the-shelf microelectronics into its systems. DoD’s purchase of specific EDA tools is siloed by the programs it funds. Separate from its use of EDA tools, DoD has also funded substantial research into future applications of EDA tools. DARPA’s Intelligence Design of Electronic

___________________

²⁸ C.T. Lopez, 2023, “DOD Names 8 Locations to Serve as New ‘Microelectronics Commons’ Hubs,” DOD News, September 20, https://www.defense.gov/News/News-Stories/Article/Article/3532338/dod-names-8-locations-to-serve-as-new-microelectronics-commons-hubs.

²⁹ J. Sawicki, 2020, “EDA in the Era of AI,” Electronic Design, January 8, https://www.electronicdesign.com/markets/automation/article/21120058/mentor-a-siemens-business-eda-in-the-era-of-ai.

Assets (IDEA) program is one example of recent DoD focus on this supply chain segment.³⁰

Fabless Design

The United States remains the worldwide leader in semiconductor design. Importantly, however, DoD has specific semiconductor design requirements that diverge from the overall focus of the commercial semiconductor industry. This includes custom (not commercial-off-the-shelf) radiation-hardened microelectronics capable of operating in space or nuclear environments. Such microelectronics form the backbone of satellite communications and data handling as well as sensors for warning, positioning, navigation, and timing related to everything from offensive to defensive capabilities.

___________________

³⁰ S.K. Lim, 2024, “Intelligent Desing of Electronic Assets (IDEA),” DARPA, https://www.darpa.mil/program/intelligent-design-of-electronic-assets.

³¹ Synopsys, 2024, “DSO.ai: Achieve PPA Targets Faster with the World’s First AI Application for Chip Design,” https://www.synopsys.com/ai/ai-powered-eda/dso-ai.html.

Custom radiation-hardened microelectronics have limited commercial appeal. A 2022 report from Deloitte estimated that, of the $660 billion global microelectronics market, radiation-hardened microelectronics only accounted for $1.5 billion.³² While used in commercial spaceflight and satellites, most radiation-hardened microelectronics are consumed by governments for military applications. A 2023 study from the Defense Science Board (DSB) found that “today’s microelectronics market is dominated by consumer-demand, rather than defense-demand, and the base of RH [radiation-hardened] and SRH [strategic radiation–hardened] suppliers has been shrinking. This shrinkage compounded by the dramatic consolidation of SOTA microelectronics manufacturing capability comprises a profound national security risk.”³³ As a result of low commercial demand, DoD access to custom mature and leading-edge, radiation-hardened microelectronics is limited: there are very few firms in the United States operating in this market, and those that do offer a relatively small selection of products. For example, within the 17 foundries that are a part of the Trusted Foundry Program, only four of them offer any radiation-hardened products and among those that do, the most advanced node is 90 nm (which was introduced roughly 20 years ago).^34,35

Importantly, however, as the commercial industry has advanced and fabless designs transition from a fin field-effect transistor (FinFET) to gate-all-around FETs (GAAFETs) and (eventually) to complementary FETs, research has demonstrated that commercially available leading-edge microelectronics have some radiation tolerance by default. Simply put, as device features get smaller, there is less opportunity for radiation-induced device upsets. The same 2023 report from DSB describes this development in detail, noting,

___________________

³² D. Stewart, D. Jarvis, C. Simons, and G. Crossan, 2022, “That’s Just Rad! Radiation-Hardened Chips Take Space Tech and Nuclear Energy to New Heights: The Next Generation of Rad-Hard Chips Is Helping Bring Devices Used in High-Radiation Environments into the 21st Century at Last,” Deloitte Insights, November 30, https://www2.deloitte.com/us/en/insights/industry/technology/technology-media-and-telecom-predictions/2023/radiation-hardened-electronics-market.html.

³³ S.A. Jackson, 2023, “Balancing Openness and Security Across the DoD Academic Research Enterprise (ARE),” Defense Science Board, August 23, https://apps.dtic.mil/sti/citations/trecms/AD1212739, Appendix C.

³⁴ OUSD, 2024, “Accredited Suppliers,” May 22, https://www.acq.osd.mil/asds/dmea/tapo/docs/tp/Accredited-Supplier-22May2024.pdf.

³⁵ M. LaPedus, 2002, “Intel Works Toward Ramp of 90-nm Process in 2003,” EE Times, February 27, https://www.eetimes.com/intel-works-toward-ramp-of-90-nm-process-in-2003.

³⁶ DSB (Defense Science Board), 2022, “Radiation-Hard Microelectronics,” JSR-21-05, https://dsb.cto.mil/reports/2020s/ARE_Final%20Report_08102023.pdf.

To better coordinate DoD radiation-hardened microelectronics equities, DoD has the Strategic Radiation-Hardened Electronics Council (SRHEC).³⁷ The SRHEC convenes representatives from across the Departments of Defense and Energy as well as the National Aeronautics and Space Administration (NASA) who manage programs that require radiation-hardened electronics. One major challenge identified by the SRHEC in recent years, in addition to domestic supply of radiation-hardened microelectronics, is domestic availability of the radiation sources and expertise needed to test microelectronics to determine their radiation hardness. The lack of infrastructure across the nation to test radiation-hardened electronics has led to greatly extended chip and system development timelines of as much as 7 years.³⁸ This challenge is echoed by an earlier National Academies of Sciences, Engineering, and Medicine report, which found that the U.S. domestic electronics radiation testing capacity was likely to continue to be oversubscribed to the increase in commercial satellites and a variety of DoD and DOE modernization programs.³⁹

___________________

³⁷ J. Franco and J. Ross, 2021, “Strategic Radiation-Hardened (SRH) Electronics Council (SRHEC) Public Summary from Analysis of Alternatives (AoA) for Domestic Single-Event Effects (SEE) Test Facilities,” Presented during VI. a. Virtual Networking Opportunity w AoA Briefing and Status session at the NASA Electronic Parts and Packaging (NEPP) Program 2021 Domestic High-Energy Single-Event Effects (SEE) Testing Users Meeting, April 13, https://nepp.nasa.gov/workshops/dhesee2021/presentations.cfm.

³⁸ Ibid.

³⁹ National Academies of Sciences, Engineering, and Medicine (NASEM), 2018, Testing at the Speed of Light: The State of U.S. Electronic Parts Space Radiation Testing Infrastructure, Washington, DC: The National Academies Press, https://doi.org/10.17226/24993.

⁴⁰ N. Pieper, Y. Xiong, A. Feeley, et al., 2022, “SRAM Multi-Cell Upset Vulnerability at the 5-nm FinFET Node,” Department of Energy, July 1, https://www.osti.gov/servlets/purl/2004056.

This national center of excellence could be tasked with increasing the availability of radiation-hardened microelectronics in the United States. It could explore the suitability of expected innovations in GAAFETs and chiplet architectures to support DoD’s radiation-hardened microelectronics needs. DoD could partner with DOC to determine if funds allocated through the CHIPS and Science Act of 2022 could be used to create the national center of excellence with the needed radiation hardness testing facilities and expertise to efficiently support ongoing demand from DoD, NASA, DOE, and the commercial spaceflight industry. DoD could ensure that this center of excellence engages with leading-edge microelectronics suppliers to evaluate their products’ potential radiation hardness and suitability to meet DoD needs.

Tool Manufacturing

The process of manufacturing semiconductors requires hundreds of sequential steps, each of which in turn relies on specialty equipment (semiconductor manufacturing equipment, or just “tools”). DoD has historically supported R&D in a variety of semiconductor manufacturing equipment technologies. Notably, DARPA funded a 15-year effort into next-generation lithographic technologies from the 1990s into the mid-2000s.⁴¹

In recent years, however, semiconductor manufacturing equipment has become increasingly capital-intensive, and the number of suppliers worldwide has consolidated to the point where there are only one to three suppliers for most major categories of tools. As a result of the increased capital expenditures necessary to compete in semiconductor manufacturing equipment and the overall consolidation

___________________

⁴¹ EE Times, 2005, “DARPA Ends Litho Aid at Critical Juncture for Maskless,” February 28, https://www.eetimes.com/darpa-ends-litho-aid-at-critical-juncture-for-maskless.

in the industry, the role of the government in supporting innovation in semiconductor manufacturing equipment has declined.

The CHIPS Act funded a $2 billion effort led by NIST to support metrology innovation.⁴² In semiconductor manufacturing, metrology tools are used to ensure that fabricated microelectronics perform as intended and, in the event they do not, assist with defect detection and mitigation. These tools are among the most specialized types of equipment used in semiconductor manufacturing, and the overall number of suppliers in the United States and worldwide is limited.^43,44 Innovation in metrology tools supports innovation in the semiconductor sector generally, including advanced packaging, chiplets, and heterogeneous integration. NIST also has recognized the importance of developing a secure ecosystem for sharing metrology data to accelerate R&D related to semiconductor technologies, with the launch of its Metrology Exchange to Innovate in Semiconductors (METIS) program.⁴⁵

___________________

⁴² NIST, 2024, “Notice of Funding Opportunity (NOFO),” https://www.nist.gov/chips/research-development-programs/metrology-program.

⁴³ KLA (Keep Looking Ahead), 2019, “KLA-Tencor Corporation to Change Name to KLA Corporation to Represent the Company’s Broader Scope and Optimistic Vision,” January 10, https://ir.kla.com/news-events/press-releases/detail/52/kla-tencor-corporation-to-change-name-to-kla-corporation-to.

⁴⁴ D. Rijnberk, 2023, “KLA Corporation: A Top Pick in the Semiconductor Industry,” Seeking Alpha, November 27, https://seekingalpha.com/article/4654256-kla-corporation-a-top-pick-in-the-semiconductor-industry.

⁴⁵ NIST, 2023, “Building a Metrology Exchange to Innovate in Semiconductors (METIS): A Vision for the CHIPS Metrology Program Data Exchange,” NIST CHIPS 1000-2 ipd, December, https://nvlpubs.nist.gov/nistpubs/CHIPS/NIST.CHIPS.1000-2.ipd.pdf.

Manufacturing Capacity and Capability

Through the CHIPS Act, Congress appropriated $39 billion to provide incentives to firms in the semiconductor industry to increase domestic production of microelectronics and support the underlying supply chain of products and services that support semiconductor manufacturing. A wide variety of firms have announced projects to create new semiconductor manufacturing capacity and capabilities in the United States. Notably, Intel, Samsung, and TSMC have announced new logic chip production facilities, Micron has announced a new memory production facility, Amkor and SK Hynix have announced new advanced packaging facilities, and a wide variety of materials and equipment suppliers are increasing domestic capacity and capabilities.

DoD stands to benefit from forthcoming increasing domestic availability of manufacturing capacity and capability. Notably, DOC has announced agreements with BAE Systems and Microchip Technology to provide financial incentives that will assist these firms’ existing supply of microelectronics to DoD. While these efforts are focused on supporting DoD suppliers of custom mature microelectronics, DoD also requires access to leading-edge microelectronics as well. As described in the first item of the committee’s statement of task, DoD’s access to leading-edge microelectronics will only be possible through partnerships with commercial firms that supply these microelectronic components.

Assembly, Testing, and Packaging

Assembly, testing, and packaging refers to the process of verifying the functionality of finished semiconductors, protecting them, and creating the structures for physically connecting them into the systems for which they are designed to be

incorporated. The semiconductor industry is currently pursuing a variety of advanced packaging efforts as Moore’s Law slows down. Advanced packaging offers increased performance, power, modularity, and durability relative to traditional packaging approaches.⁴⁶ All of these attributes are of value to DoD as well as to the commercial sector.

DoD is thus similarly funding efforts to explore and leverage the promise of advanced packaging architectures for microelectronics. Notably, DoD has created the State-of-the-Art Heterogeneous Integrated Packaging (SHIP) Program specifically focused on creating a pathway to integrate commercial state-of-the-art packaging technologies for DoD systems.⁴⁷ This partnership leverages packaging innovations from Intel and Qorvo, which provide microelectronics to BAE Systems for integration in DoD systems. For example, Qorvo is reportedly supplying microelectronics that “provide form, fit, and function replacement of a legacy chip and wire design, resulting in significant production cost savings, reduced footprint, and improved performance.”⁴⁸

___________________

⁴⁶ J. VerWey, 2022, “Re-Shoring Advanced Semiconductor Packaging: Innovation, Supply Chain Security, and U.S. Leadership in the Semiconductor Industry,” CSET, June, https://cset.georgetown.edu/publication/re-shoring-advanced-semiconductor-packaging.

⁴⁷ DoD, 2023, “Department of Defense Celebrates Advancements in Microelectronics Packaging Capabilities,” April 6, https://www.defense.gov/News/Releases/Release/Article/3355049/department-of-defense-celebrates-advancements-in-microelectronics-packaging-cap.

⁴⁸ Ibid.